ATMEGA64A-MN Atmel, ATMEGA64A-MN Datasheet - Page 138

• Manufacturer Part Number: ATMEGA64A-MN
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.11.9
15.11.10 OCR1BH and OCR1BL – Output Compare Register 1 B
15.11.11 OCR1CH and OCR1CL – Output Compare Register 1 C
15.11.12 OCR3AH and OCR3AL – Output Compare Register 3 A
15.11.13 OCR3BH and OCR3BL – Output Compare Register 3 B
15.11.14 OCR3CH and OCR3CL – Output Compare Register 3 C
8160C–AVR–07/09
OCR1AH and OCR1AL –Output Compare Register 1 A
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers.
Bit
0x2B (0x4B)
0x2A (0x4A)
Read/Write
Initial Value
Bit
0x29 (0x49)
0x28 (0x48)
Read/Write
Initial Value
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x87)
(0x86)
Read/Write
Initial Value
Bit
(0x85)
(0x84)
Read/Write
Initial Value
Bit
(0x83)
(0x82)
Read/Write
Initial Value
See “Accessing 16-bit Registers” on page 114.
R/W
R/W
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
OCR1B[15:8]
4
0
4
0
OCR3B[15:8]
OCR3C[15:8]
OCR1A[15:8]
OCR1C[15:8]
OCR3A[15:8]
OCR1B[7:0]
OCR3B[7:0]
OCR3C[7:0]
OCR1A[7:0]
OCR1C[7:0]
OCR3A[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
1
0
1
0
ATmega64A
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
OCR1BH
OCR3BH
OCR3CH
OCR1AH
OCR1BL
OCR1CH
OCR3AH
OCR3BL
OCR3CL
OCR1AL
OCR1CL
OCR3AL
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