ATMEGA64A-MN Atmel, ATMEGA64A-MN Datasheet - Page 171

• Manufacturer Part Number: ATMEGA64A-MN
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.5
19.5.1
8160C–AVR–07/09
Register Description
SPCR – SPI Control Register
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
CPOL functionality is summarized below:
Table 19-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
example. The CPHA functionality is summarized below:
Table 19-4.
Bit
0x0D (0x2D)
Read/Write
Initial Value
CPOL
CPHA
0
1
0
1
CPOL Functionality
CPHA Functionality
SPIE
R/W
7
0
Figure 19-3 on page 170
SPE
R/W
6
0
Leading Edge
DORD
Leading Edge
R/W
5
0
Figure 19-3 on page 170
Falling
Rising
Sample
Setup
MSTR
R/W
4
0
and
Figure 19-4 on page 170
CPOL
R/W
3
0
CPHA
and
R/W
2
0
Figure 19-4 on page 170
SPR1
R/W
Trailing Edge
Trailing Edge
1
0
ATmega64A
Sample
Falling
Rising
Setup
for an example. The
SPR0
R/W
0
0
SPCR
for an
171