ATMEGA64A-MN Atmel, ATMEGA64A-MN Datasheet - Page 141

• Manufacturer Part Number: ATMEGA64A-MN
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.11.19 TIFR – Timer/Counter Interrupt Flag Register
15.11.20 ETIFR – Extended Timer/Counter Interrupt Flag Register
8160C–AVR–07/09
Note:
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 2 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOV1 flag is set when the timer overflows. Refer to
flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
• Bit 7:6 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be set to zero when ETIFR is written.
Bit
0x36 (0x56)
Read/Write
Initial Value
Bit
(0x7C)
Read/Write
Initial Value
1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described
in this section. The remaining bits are described in their respective timer sections.
OCF2
R/W
R/W
7
–
0
7
0
R/W
TOV2
6
–
0
R/W
6
0
ICF3
R/W
(1)
5
0
ICF1
R/W
5
0
OCF3A
R/W
4
0
OCF1A
R/W
4
0
OCF3B
R/W
3
0
OCF1B
R/W
3
0
TOV3
R/W
Table 15-5 on page 135
2
0
TOV1
R/W
2
0
OCF3C
R/W
1
0
OCF0
R/W
1
0
OCF1C
R/W
ATmega64A
0
0
TOV0
R/W
0
0
ETIFR
for the TOV1
TIFR
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