ATMEGA64A-MN Atmel, ATMEGA64A-MN Datasheet - Page 226

• Manufacturer Part Number: ATMEGA64A-MN
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.9
21.9.1
21.9.2
8160C–AVR–07/09
TWI Register Description
TWBR –TWI Bit Rate Register
TWCR – TWI Control Register
This is summarized in
Figure 21-21. Possible Status Codes Caused by Arbitration
• Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 202
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
Bit
(0x70)
Read/Write
Initial Value
Bit
(0x74)
Read/Write
Initial Value
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
START
TWBR7
TWINT
R/W
R/W
7
0
7
0
for calculating bit rates.
Address / General Call
Figure
TWBR6
TWEA
R/W
R/W
Direction
received
6
0
6
0
Own
Yes
Arbitration lost in SLA
SLA
21-21. Possible status values are given in circles.
Read
Write
TWBR5
TWSTA
R/W
R/W
5
0
5
0
No
TWBR4
TWSTO
R/W
R/W
4
0
4
0
68/78
38
B0
TWBR3
Arbitration lost in Data
TWWC
R/W
R
3
0
3
0
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
TWBR2
TWEN
R/W
R/W
2
0
2
0
Data
TWBR1
R/W
R
1
0
1
–
0
ATmega64A
“Bit Rate Generator
TWBR0
TWIE
R/W
R/W
0
0
0
0
STOP
TWBR
TWCR
226