M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet
M1AFS-EMBEDDED-KIT
Specifications of M1AFS-EMBEDDED-KIT
Related parts for M1AFS-EMBEDDED-KIT
M1AFS-EMBEDDED-KIT Summary of contents
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Cortex-M1 v3.1 Handbook ...
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... Actel. Actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or fitness for a particular purpose. Information in this document is subject to change without notice. Actel assumes no responsibility for any errors that may appear in this document. This document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of Actel Corporation ...
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... Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Supported Actel FPGA Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 Cortex-M1 Overview Cortex-M1 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Cortex-M1 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Delivery and Deployment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Tightly Coupled Memory (TCM) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 Cortex-M1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory Map ...
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... Table of Contents A Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Actel Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Actel Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Upward-compatible with Cortex-M3 Supported Actel FPGA Families The Cortex-M1 version part number prefix is in parentheses. ® • IGLOO (M1AGL) • IGLOOe (M1AGLE) • ProASIC3L (M1A3PxxxxL) ® • ProASIC 3 (M1A3P) • ProASIC3E (M1A3PE) • Fusion (M1AFS) ® code Revision 12 ® Cortex™-M1 ree-stage 5 ...
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... Utilization and Performance Cortex-M1 can be implemented in several Actel FPGA devices. synthesis tools. The Configuration column of using standard particular configurations of the core. Refer to configuration. Table 1 • Cortex-M1 Utilization and Performance Data Device M1AFS250 M1AFS600 M1AFS1500 M1AGL250V2 M1AGL250V5 M1AGL600V2 M1AGL600V5 M1AGL1000V2 M1AGL1000V5 M1AGLE3000V2 M1AGLE3000V5 M1A3P250 ...
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... If you configure Cortex-M1 to enable debugging via the UJTAG macro (which is the necessary configuration when debugging with Actel's SoftConsole tool good practice to ensure that low skew routing is used for the clock signal output from the UJTAG macro. You may also wish to use low skew routing for the reset signal from the UJTAG macro, but this is a less critical signal ...
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Introduction assign_quadrant_clock -net <hierarchical path to Cortex-M1 instance>/RS/UDRCK -quadrant LR If your SmartDesign component is the top-level module in your design and you have accepted the default instance name of CortexM1Top_0 for Cortex-M1, the previous example PDC constraint will have ...
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... Debug Interface (JTAG) Misc Debug . Signals Key Figure 1-1 • Cortex-M1 Block Diagram Figure 1-1 and include the processor core, the Nested ng an M1AFS1500 or M1A3PE1500 device. CortexM1Top Preconfigured, Placed and Routed (CDB file) Black Box SYSRESETn Reset Synch. DBGRESETn Debug Logic ...
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... Currently, configurations which minimize the resource requirements of the core are available for each M1-enabled device. For the M1AFS1500 and M1A3PE1500 devices, a more fully featured configuration can be selected. In all cases the core can be configured to include or exclude debug logic intended that, over time, more configurations will become available across a range of devices. Each configuration is assigned a unique number for ease of reference ...
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The configurations listed in the configuration of the logic within the black box CDB, which accounts for the majority of the Cortex-M1 logic. There is also some configurability associated with the top-level RTL wrapper surrounding the CDB. A GUI configuration ...
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... JTAG, using UJTAG macro has been selected, the JTAG pins must still be routed to the top level of your design, but in this case specific pin assignments are not required. Actel's Designer tool will recognize that the UJTAG macro is in use and make use of the dedicated JTAG pins of the device for the Cortex-M1 debug connection ...
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Table 1-2 • Cortex-M1 Port Descriptions (continued) LOCKUP 1 Output Status output which, when asserted, indicates that the processor is in the lock-up state. HALTED 1 Output Status output which, when asserted, indicates that the processor is in halting debug ...
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Cortex-M1 Overview Table 1-2 • Cortex-M1 Port Descriptions (continued) nTRST 1 TMS 1 TDI 1 TDO 1 14 Input JTAG reset signal, active low. This input is only functional when the core has been configured to include debug. Input JTAG ...
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Interfaces The Cortex-M1 processor has an external AHB-Lite interface that can be used to connect to other AMBA components. Internally a private peripheral bus (PPB) is used to facilitate communication between the processor core and the NVIC and ...
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... Note: ITCM and DTCM are currently fixed at 0 memory size in the majority of Actel M1 devices. TCMs are supported on the M1AFS1500 and M1A3PE1500 devices. 16 shows the signal timings for ITCM. The DTCM signal timings are the same as ...
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... The stack pointer (R13) becomes a banked register when OS extensions are present. Note: OS extensions are not supported on the majority of Actel M1 devices. OS extensions are supported on the M1AFS1500 and M1A3PE1500 devices. Data Types The processor supports the following data types: • ...
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Cortex-M1 Features Registers The processor has the following 32-bit registers (shown in • 13 general purpose registers, R0 • Stack Pointer (SP), R13 • Link Register (LR), R14 • Program Counter (PC), R15 • Program status registers, xPSR Low Registers ...
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Special Purpose Program Status Registers (xPSR) Processor status at the system level is broken into three categories and can be accessed as individual registers, a combination of any two of the three combination of all three using the ...
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Cortex-M1 Features Memory Map Cortex-M1 has a defined memory map with the various processor interfaces addressed by different memory map regions, as shown in map with the exception of the reserved regions. The reserved regions are Execute Never (XN) and ...
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... ARM processors. The processor contains a configuration option that enables the user to select either the little-endian or big-endian format during implementation. Currently, only little-endian configurations of Cortex-M1 are supported on Actel devices. Subsystem Restrictions The fixed memory map of the Cortex-M1 places certain restrictions on the processor subsystem. ...
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Cortex-M1 Features Exception Types The types of exceptions supported in Cortex-M1 are listed in results from an error condition. Faults can be reported synchronously or asynchronously to the instruction that caused them. In general, faults are reported synchronously. Faults caused ...
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Servicing an Exception When the processor invokes an exception, it automatically pushes the following eight registers in two stages to the stack in the following order: 1. Processor Status Register (xPSR) 2. ReturnAddress () 3. Link Register (LR) 4. R12 ...
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Cortex-M1 Features Figure 3-4 shows a timing example of an exception entry without wait states. CLK TCMADDR RIA TCMWDATA TCMRDATA RI TCMWR Figure 3-4 • Exception Entry Without Wait States After returning from the exception, the processor automatically pops the ...
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... NVIC latches the pending bit. After the ISR activates, the pending bit is cleared. After the bit is cleared if the interrupt is asserted again while it is activated, it can latch the pending bit again. Note: The number of external interrupts is currently fixed the majority of Actel M1 devices. A processor configuration with 16 external interrupts is available for the M1AFS1500 and M1A3PE1500 devices. Clocking and Resets Clocks HCLK is the main clock input and clocks the majority of the logic in the processor ...
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Cortex-M1 Features DBGRESETn DBGRESETn resets debug logic which is clocked by HCLK and the source of its assertion is dependent on the setting chosen for the Reset to debug logic (DBGRESETn) option. When this option is set to Driven by ...
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... IAR. The RealView and IAR tools feature compilers that offer a higher level of efficiency than the GCC compiler included in SoftConsole. If higher code density is required for an application than what can be achieved using GNU, Actel recommends that one of these other tools be purchased and used ...
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Cortex-M1 Design Entry Flow Libero IDE automatically manages Cortex-M1 through the tool flow when it is instantiated in a SmartDesign project system design. The design can consist of only the Cortex-M1 itself or it can include a range ...
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... The majority of the Cortex-M1 core is contained within a black box CDB file that allows users to access the top level I/O and use the core in Actel M1 devices, but not view the contents of the black box. The black box cannot be unlocked and can only be programmed into an Actel M1 device. The CDB file includes placement and routing information meaning that the location of the processor is fixed within the FPGA fabric of the target device ...
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Bus Functional Model (BFM) During the development of an FPGA-based SoC, various stages of testing can be performed. This may involve some or all of the following approaches: • Hardware simulation, using Verilog or VHDL • Software simulation, ...
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Bus Functional Model (BFM) BFM Usage Flow The BFM is part of an overall system test strategy helpful to look at the context in which it is used. Figure 6-1 shows the various components within a typical ...
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It has knowledge of whether registers are read-only, read/write, clear- on-read, or write-only. From this it can decide what the expected data should be on reads. The system Verilog/VHDL can be edited to add new design blocks ...
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Bus Functional Model (BFM) Syntax write width resource_name byte_offset data; Width This takes on the enumerated values for word, halfword, or byte respectively. resource_name This is a string containing the user-friendly instance name of the ...
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Readcheck The readcheck command causes the BFM to perform a read of a specified offset, within the memory map range of a specified system resource and to compare the read value with the expected value provided. Syntax readcheck width resource_name ...
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... Actel IP cores: the Core10/100 and the CoreUART. SPIRIT IP-XACT Attributes SmartDesign has access to a database of Actel IP cores and a list of attributes for each core. These attributes are organized according to the SPIRIT IP-XACT specification in XML. For example, in the case of the CoreUART, the attributes would indicate that there are three registers, as shown in Table 6-1 • ...
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Debug The ARM Debug Architecture uses a protocol converter box to allow the debugger to talk via a JTAG port directly to the core. About Debug Debug facilitates the following: • Core halt • Core stepping • Core ...
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... Debug JTAG Debug Interface The Actel FlashPro3 programmer, which is used to program the FPGA and debug the Cortex-M1 core using SoftConsole, uses a standard 10-pin JTAG interface, shown in including those in the RealView and IAR tools, use a 20-pin, 2.54 mm pitch IDC connector page 38). The cable can be used to mate with a keyed box header on the target. ...
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... Test Data In signal from RealView ICE to the target JTAG port. Actel recommends pulling this pin HIGH on the target. TDO Input Test Data Out from the target JTAG port to RealView ICE. Actel recommends pulling this pin HIGH on the target. TMS Output Test Mode signal from RealView ICE to the target JTAG port. This pin must be pulled HIGH on the target to avoid adverse effects from any spurious TCKs when there is no connection ...
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AC Parameters This section gives the AC timing parameters of the Cortex-M1 black box across all M1-enabled devices. These numbers describe the timing at the ports of the black box; that is, the logic contained within the CDB ...
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AC Parameters AC Parameters Table 8-1 • AC Parameters for Cortex-M1 Black Box on ProASIC3 Devices Parameter Clock Signal PERIOD HCLK – PERIOD SWCLKTCK – SETUP HCLK HRDATA SETUP HCLK HREADY SETUP HCLK HRESP SETUP HCLK IRQ SETUP HCLK NMI ...
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Table 8-2 • AC Parameters for Cortex-M1 Black Box on ProASIC3E Devices Parameter Clock Signal PERIOD HCLK PERIOD SWCLKTCK SETUP HCLK HRDATA SETUP HCLK HREADY SETUP HCLK HRESP SETUP HCLK SETUP HCLK SETUP HCLK SYSRESETn CLOCK2OUT HCLK HADDR CLOCK2OUT HCLK ...
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AC Parameters Table 8-3 • AC Parameters for Cortex-M1 Black Box on ProASIC3L Devices Parameter Clock Signal PERIOD HCLK – PERIOD SWCLKTCK – SETUP HCLK HRDATA SETUP HCLK HREADY SETUP HCLK HRESP SETUP HCLK IRQ SETUP HCLK NMI SETUP HCLK ...
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... M1AFS1500 M1AFS1500 M1AFS1500 028911 134820 16.197 21.773 11.692 21.773 1.147 5.885 1.793 4.532 6.21 5.194 5.575 5.121 4.569 1.546 3.118 5.02 3.171 2.032 2 ...
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AC Parameters Table 8-5 • AC Parameters for Cortex-M1 Black Box on IGLOO Devices (Part 1) Parameter Clock Signal PERIOD HCLK PERIOD SWCLKTCK SETUP HCLK HRDATA SETUP HCLK HREADY SETUP HCLK HRESP SETUP HCLK IRQ SETUP HCLK NMI SETUP HCLK ...
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Table 8-6 • AC Parameters for Cortex-M1 Black Box on IGLOO Devices (Part 2) M1AGL1000V2 M1AGL1000V5 M1AGL1000V5 M1AGLE3000V2 M1AGLE3000V2 M1AGLE3000V5 M1AGLE3000V5 Parameter Clock Signal PERIOD HCLK PERIOD SWCLKTCK SETUP HCLK HRDATA SETUP HCLK HREADY SETUP HCLK HRESP SETUP HCLK IRQ ...
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... Ordering Information Ordering Codes Cortex-M1 can be ordered through your local Actel sales representative. It should be ordered using the following number scheme: CortexM1-XX, where XX is listed in Table 9-1 • Ordering Codes XX OM Note: CortexM1-OM is included free with a Libero IDE license Table 9-1. ...
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... Figure 1-1 • Cortex-M1 Block and Figure 1-2 • M1 Configuration Window chapter. "Cortex-M1 I/O Ports" was updated. "Cortex-M1 Features" chapter were revised, clarifying OS Flow", "Bus Functional Model Page N/A for the M1AFS1500 new and Table 1-2 • 12 ...
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... Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the Actel web site. Website You can browse a variety of technical and non-technical information on Actel’s home page, at www.actel.com. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center from 7:00 a ...
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... The phone hours are from 7:00 a.m. to 6:00 p.m., Pacific Time, Monday through Friday. The Technical Support numbers are: 650.318.4460 800.262.1060 Customers needing assistance outside the US time zones can either contact technical support via email (tech@actel.com) or contact a local sales office. Sales office listings can be found on the website at www.actel.com/company/contact/default.aspx sio ...
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... S supported Actel FPGA families utilization and performance 6 T technical support 53 Tightly Coupled Memory interface timing shell 35 W ...
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... Fax +44 (0) 1276 607 540 © 2010 Actel Corporation. All rights reserved. Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. ...