M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 31

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6 – Bus Functional Model (BFM)
During the development of an FPGA-based SoC, various stages of testing can be performed. This may
involve some or all of the following approaches:
Due to the rapid prototyping capability of FPGAs, integration of hardware and software often occurs
earlier in the development cycle than it would for ASIC targets. Therefore, hardware and software co-
verification (which can be very slow) are not as critical an issue for most FPGA-based system-level
designs.
SmartDesign provides a means for stitching together IP blocks to create a system. When this system is
generated within SmartDesign, a system testbench is also created to aid simulation of the design. In the
case of a Cortex-M1 based system, a bus functional model (BFM) of the processor is generated by
SmartDesign for use during simulation. Essentially this BFM takes the place of the Cortex-M1 black box
during simulation as the black box is not amenable to simulation. SmartDesign also creates script files for
controlling the BFM.
This section describes the following aspects of Cortex-M1 BFM:
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Hardware simulation, using Verilog or VHDL
Software simulation, using a host-based instruction set simulator (ISS) of the processor
Hardware and software co-verification, using a full functional model of the processor in Verilog or
VHDL form, or using a tool such as Seamless
Functionality
BFM usage flow
BFM script language
Platforms
Supported simulation tools
Example BFM use case
R ev i si o n 1 2
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