M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 13

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-2 • Cortex-M1 Port Descriptions (continued)
LOCKUP
HALTED
NMI
IRQ0
IRQ1 to IRQ7
IRQ8 to IRQ15
IRQ16 to IRQ31
HADDR
HBURST
HPROT
HRDATA
HREADY
HRESP
HSIZE
HTRANS
HWDATA
HWRITE
HMASTLOCK
EDBGRQ
JTAGTOP
JTAGNSW
SWDO
SWDOEN
nTDOEN
TCK
1
1
1
1
1
1
1
1
1
32
32
32
1
1
1
1
3
4
1
2
3
2
Output AHB-Lite transfer direction indication. High for a write transfer.
Output AHB-Lite signal that indicates if a transfer is part of a locked
Input
Output Indicates state of JTAG controller. This output is only functional
Output Indicates whether JTAG or Serial Wire (SW) based debug is in
Output Serial data output. This output is only functional when the core has
Output Active high serial data output enable. This output is only functional
Output Active low output enable for JTAG TDO signal. This output is only
Input
Output Status output which, when asserted, indicates that the processor is
Output Status output which, when asserted, indicates that the processor is
Output AHB-Lite address bus
Output AHB-Lite burst indication
Output AHB-Lite protection control signals
Output AHB-Lite size indication; byte, halfword, word, for example.
Output AHB-Lite transfer type indication. Can be IDLE, BUSY,
Output AHB-Lite write data bus
Input
Input
Input
Input
Input
Input
Input
Input
in the lock-up state.
in halting debug mode. This output is only functional when the core
has been configured to include debug logic.
Non-maskable interrupt
External interrupt 0
External interrupts 1 to 7. These are only functional when the core
has been configured with 8 or more interrupts.
External interrupts 8 to 15. These are only functional when the
core has been configured with 16 or more interrupts.
External interrupts 16 to 31. These are only functional when the
core has been configured with 32 interrupts.
AHB-lite read data bus
AHB-Lite "bus ready" signal
AHB-Lite response signal; indicates OKAY or ERROR status for
each transfer on the bus.
NONSEQUENTIAL, or SEQUENTIAL.
sequence.
External debug request. This input is only functional when the core
has been configured to include debug logic.
when the core has been configured to include debug.
use. High = JTAG, low = SW. This output is only functional when
the core has been configured to include debug.
been configured to include debug.
when the core has been configured to include debug.
functional when the core has been configured to include debug.
JTAG clock input. This input is only functional when the core has
been configured to include debug.
R ev i si o n 1 2
Cortex-M1 v3.1 Handbook
13