M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 26

MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit

M1AFS-EMBEDDED-KIT

Manufacturer Part Number
M1AFS-EMBEDDED-KIT
Description
MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
Manufacturer
Actel
Datasheet

Specifications of M1AFS-EMBEDDED-KIT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Cortex-M1 Features
26
DBGRESETn
DBGRESETn resets debug logic which is clocked by HCLK and the source of its assertion is dependent
on the setting chosen for the Reset to debug logic (DBGRESETn) option. When this option is set to
Driven by NSYSRESET input, DBGRESETn is asserted when NSYSRESET is asserted. When this
option is set to Driven by PORESETN input, DBGRESETn is asserted when PORESETN is asserted.
WDOGRESn
WDOGRESn is a reset output suitable for connection to a watchdog component such as CoreWatchdog.
WDOGRESn is asserted when any of the following signals assert:
Buffering of Clocks and Resets
Buffers are included within the CortexM1Top level of hierarchy to ensure that low skew routing resources
are used for clock and reset signals. One important exception to this is the HCLK signal. HCLK is not
buffered within the core; you must ensure that the signal driving the HCLK input to the core is driven by a
CLKINT buffer.
NSYSRESET (external push button reset)
PORESETN (power-on reset signal)
SYSRESETREQ (reset request signal from processor core)
R ev i sio n 1 2

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