M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 10

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Cortex-M1 Overview
Cortex-M1 Configurations
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The NVIC is closely coupled to the Cortex-M1 core to achieve low-latency interrupt processing. The
processor state is automatically saved on interrupt entry and restored on interrupt exit, with no instruction
overhead to simplify software development.
The 16-bit length of the Cortex-M1 Thumb instruction allows it to approach twice the code density of the
standard 32-bit ARM code, while retaining most of the ARM performance advantages over a traditional
16-bit processor that uses 16-bit registers. This is possible because Thumb code operates on the 32-bit
register set in the processor. Thumb code is able to provide up to 65% of the code size of ARM, and
160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
Detailed information on the Cortex-M1 processor is contained in the Cortex-M1 Technical Reference
Manual (TRM). This document is available on the ARM website (www.arm.com) and is also delivered
with the core. Right-click on the core in the Libero Catalog pane and select Open documentation >
CortexM1_TRM.pdf to open the document.
The information in the Cortex-M1 TRM applies to the level of hierarchy contained within the blue box
shown in
Due to the fact that much of the logic in the Cortex-M1 is contained within the black box CDB, the extent
of configurability available to the user is limited; essentially, canned configurations are presented for use.
Currently, configurations which minimize the resource requirements of the core are available for each
M1-enabled device. For the M1AFS1500 and M1A3PE1500 devices, a more fully featured configuration
can be selected. In all cases the core can be configured to include or exclude debug logic. It is intended
that, over time, more configurations will become available across a range of devices. Each configuration
is assigned a unique number for ease of reference;
with the corresponding configuration numbers.
Table 1-1 • Cortex-M1 Configurations
Configuration
Number
028910
028911
134820
134821
Figure 1-1 on page
Little endian, 1 interrupt, small multiplier, OS extensions
absent, 0 KB ITCM, 0 KB DTCM, debug logic not included
Little endian, 1 interrupt, small multiplier, OS extensions
absent, 0 KB ITCM, 0 KB DTCM, reduced debug with JTAG
interface
Little endian, 16 interrupts, normal multiplier, OS extensions
present, 8 KB ITCM, 4 KB DTCM, debug logic not included
Little endian, 16 interrupts, normal multiplier, OS extensions
present, 8 KB ITCM, 4 KB DTCM, reduced debug with JTAG
interface
9; that is, at the level of the black box CDB.
Configuration Description
R ev i sio n 1 2
Table 1-1
shows the available configurations along
All M1-enabled devices
All M1-enabled devices
Devices on which
Configuration is
M1A3PE1500
M1A3PE1500
M1AFS1500,
M1AFS1500,
Available