VNC2-48Q1B-REEL FTDI, VNC2-48Q1B-REEL Datasheet - Page 31

• Manufacturer Part Number: VNC2-48Q1B-REEL
• Description: USB Interface IC Vinculum-II Dual USB Host/Dev IC QFN-48
• Manufacturer: FTDI
• Type: USB Host/Device Controllerr

Specifications of VNC2-48Q1B-REEL

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 25 mA
• Operating Supply Voltage: 1.8 V, 3.3V
• Package / Case: QFN-48
• Description/function: USB Vinculum-II Dual Host/Dev IC QFN-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: VINCULUM2

5.1 I/O Peripherals Signal Names
Peripheral
Table 8 I/O Peripherals Signal Names
Note: # is used to indicate an active low signal.
Debugger
SPI Slave
SPI Slave
Master
UART
GPIO
FIFO
PWM
SPI
0
1
uart_tx_active
spi_m_ss_0#
spi_m_ss_1#
Signal Name
spi_s0_mosi
spi_s0_miso
spi_s1_mosi
spi_s1_miso
spi_m_mosi
spi_m_miso
spi_s0_ss#
spi_s1_ss#
fifo_clkout
spi_s0_clk
spi_s1_clk
uart_dcd#
uart_dsr#
spi_m_clk
uart_dtr#
uart_cts#
uart_rts#
fifo_txe#
fifo_data
debug_if
fifo_rxf#
fifo_wr#
uart_txd
uart_rxd
fifo_oe#
uart_ri#
fifo_rd#
pwm
gpio
Copyright © 2010 Future Technology Devices International Limited
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Outputs
40
1
1
1
1
1
0
0
0
0
0
8
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
1
1
8
Inputs
40
1
0
0
0
0
1
1
1
1
1
8
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
Description
debugger interface
Transmit asynchronous data output
Request to send control output
Data acknowledge (data terminal ready control) output
Enable transmit data for RS485 designs
Receive asynchronous data input
Clear to send control input
Data request (data set ready control) input
Ring indicator control input
Data carrier detect control input
FIFO data bus
When high, do not write data into the FIFO. When low,
data can be written into the FIFO by strobing WR high,
then low.
When high, do not read data from the FIFO. When low,
there is data available in the FIFO which can be read by
strobing RD# low, then high.
Writes the data byte on the D0...D7 pins into the
transmit FIFO buffer when WR goes from high to low.
Enables the current FIFO data byte on D0...D7 when
low. Fetches the next FIFO data byte (if available) from
the receive FIFO buffer when RD# goes from high to
low
FIFO output enable – synchronous FIFO only
FIFO clock out – synchronous FIFO only
General purpose I/O
SPI clock input – slave 0
SPI chip select input – slave 0
SPI master out serial in – slave 0
SPI master in slave out – slave 0
SPI clock input – slave 1
SPI chip select input – slave 1
Master out slave in – slave 1
Master in slave out – slave 1
SPI clock input – master
Master out slave in - master
Master in slave out - master
Active low slave select 0 from master to slave 0
Active low slave select 1 from master to slave 1
Pulse width modulation
Document No.: FT_000138
Clearance No.: FTDI#
Version -
143
1.2
31