ATTINY861-20PU Atmel, ATTINY861-20PU Datasheet - Page 125
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ATTINY861-20PU
Manufacturer Part Number
ATTINY861-20PU
Description
Microcontrollers (MCU) 8kB Flash 0.512kB EEPROM 16 I/O Pins
Manufacturer
Atmel
Specifications of ATTINY861-20PU
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/SPI/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
8 KB
Package / Case
PDIP-20
Controller Family/series
AVR Tiny
Core Size
8 Bit
No. Of I/o's
16
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Package
20PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
Ram Size
512 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY861-20PU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATTINY861-20PU ES
Manufacturer:
ATMEL
Quantity:
215
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13. USI – Universal Serial Interface
13.1
13.2
2588E–AVR–08/10
Features
Overview
•
•
•
•
•
•
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in
refer to
Register and bit locations are listed in the
Figure 13-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) is directly accessible via the data bus and contains the
incoming and outgoing data. The register has no buffering so the data must be read as quickly
as possible to ensure that no data is lost. The data register is a serial shift register where the
most significant bit is connected to one of two output pins depending of the wire mode configura-
tion. A transparent latch between the output of the data register and the output pin delays the
change of data output to the opposite clock edge of the data input sampling. The serial input is
always sampled from the Data Input (DI) pin, regardless of the configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“Pinout ATtiny261/461/861 and ATtiny261V/461V/861V” on page
USIDR
USICR
USIDB
USISR
2
4-bit Counter
3
2
1
0
3
2
1
0
D Q
LE
“Register Descriptions” on page
[1]
TIM0 COMP
Figure 13-1
0
1
Two-wire Clock
Control Unit
For actual placement of I/O pins
CLOCK
HOLD
2. Device-specific I/O
132.
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
125
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