ATTINY861-20PU Atmel, ATTINY861-20PU Datasheet - Page 41

• Manufacturer Part Number: ATTINY861-20PU
• Description: Microcontrollers (MCU) 8kB Flash 0.512kB EEPROM 16 I/O Pins
• Manufacturer: Atmel

Specifications of ATTINY861-20PU

• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire/SPI/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Package / Case: PDIP-20
• Controller Family/series: AVR Tiny
• Core Size: 8 Bit
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Ram Size: 512 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. System Control and Reset
8.0.1
2588E–AVR–08/10
Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in
reset circuitry are given in
Figure 8-1.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
BODLEVEL [1..0]
Reset Logic
Pull-up Resistor
FILTER
SPIKE
Table 19-4 on page
CKSEL[1:0]
Power-on Reset
Figure 8-1
Reset Circuit
SUT[1:0]
Brown-out
Watchdog
Oscillator
Generator
Circuit
Clock
shows the reset logic. Electrical parameters of the
CK
190.
Register (MCUSR)
MCU Status
DATA BUS
“Clock Sources” on page
Delay Counters
TIMEOUT
25.
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