MPC8536BVTAVL Freescale Semiconductor, MPC8536BVTAVL Datasheet - Page 125

Microprocessors (MPU) 8536 INDUSTRIAL 1500

MPC8536BVTAVL

Manufacturer Part Number
MPC8536BVTAVL
Description
Microprocessors (MPU) 8536 INDUSTRIAL 1500
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8536BVTAVL

Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
1500 MHz
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
0 C
Package / Case
FCPBGA-783
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8536BVTAVLA
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MPC8536BVTAVLA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
6
The following documents are required for a complete description of the device and are needed to design properly with the part.
7
Table 85
Freescale Semiconductor
Revision
3.
4.
5.
6.
7.
3
2
1
0
Maximum solder ball diameter measured parallel to datum A
Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
Capacitors may not be present on all devices
Caution must be taken not to short exposed metal capacitor pads on package top.
All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
MPC8536E PowerQUICC III Integrated Processor Reference Manual (document number: MPC8536ERM)
e500 PowerPC Core Reference Manual (document number: E500CORERM)
provides a revision history for the MPC8535E hardware specification.
Product Documentation
Document Revision History
11/2010
09/2009
09/2009
08/2009
Date
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Note:
Note: Updated
• In
• Updated
• Updated
• In
• Added Note 6 regarding USB n _DIR pin to
• In
• In
• In
• In
• Updated Die value and Bump/Underfill value in
• In
• In
• In
• Initial public release.
Bus(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is
required...”
In addition, updated footnote 26 and added footnote 29 to PCI1_AD.
MDIO/MDC.
UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration.”
LSTSEF to LSTSE for Note 4.
Table
Section 1, “Pin Assignments and Reset
Table
Table
Table
Table
Table
Table
Table
MPC8535E FC-PBGA,” and its notes.
1, “MPC8535E Pinout Listing,” added the following note: “For systems that boot from Local
44, “MII Management DC Electrical Characteristics,” changed the Voh/Vol values for
64, “I2C AC Electrical Specifications,” updated footnote 2.
82, ,
40, “SGMII DC Receiver Electrical Characteristics,” changed LSTSAB to LSTSA and
3, “Recommended Operating Conditions,” for V
5, “MPC8535E Power Dissipation 5,” remove note 5.
5, ”MPC8535E Power Dissipation 5,” changed an “—”’ to “0.”
Table 21
Figure
Figure
Table 85. Document Revision History
Table
25, “RGMII and RTBI AC Timing and Multiplexing Diagrams.”
83, ,
81, “Mechanical Dimensions and Bottom Surface Nomenclature of the
Table
84, added the Revision Level A for Rev 1.2
Substantive Change(s)
States,”updated the first sentence of the note to say, “The
Table
Mechanical Dimensions of the MPC8535E FC-PBGA
Table 84
47, “USB General Timing Parameters6.”
DD_CORE,
removed 1.1 ± 55 mV.
125

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