MPC8536BVTAVL Freescale Semiconductor, MPC8536BVTAVL Datasheet - Page 97

• Manufacturer Part Number: MPC8536BVTAVL
• Description: Microprocessors (MPU) 8536 INDUSTRIAL 1500
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTAVL

• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1500 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Package / Case: FCPBGA-783
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.20.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase
noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz
is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock
driver should be 50 ohms to match the transmission line and reduce reflections which are a source of noise to the system.
Table 69
Freescale Semiconductor
At recommended operating conditions with XV
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
Differential Input Low Voltage
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See
mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See
V
V
SD n _REF_CLK
SD n _REF_CLK
IH
IL
= –200 mV
= +200 mV
describes some AC parameters common to SGMII and PCI Express protocols.
0.0 V
AC Requirements for SerDes Reference Clocks
–
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Figure 66. Differential Measurement Points for Rise and Fall Time
Parameter
Table 69. SerDes Reference Clock Common AC Parameters
Rise Edge Rate
DD_SRDS1
Figure
Figure
or XV
67.
DD_SRDS2
66.
= 1.0V ± 5%.
Rise Edge Rate
Fall Edge Rate
Matching
Rise-Fall
Symbol
V
V
IH
IL
Fall Edge Rate
+200
Min
1.0
1.0
—
—
High-Speed Serial Interfaces
–200
Max
4.0
4.0
20
—
V/ns
Unit
V/ns
mV
mV
%
Notes
2, 3
2, 3
1, 4
2
2
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