LCMXO640C-3MN100C Lattice, LCMXO640C-3MN100C Datasheet - Page 10

• Manufacturer Part Number: LCMXO640C-3MN100C
• Description: CPLD - Complex Programmable Logic Devices 640 LUTs 74 IO 1.8/2 .5/3.3V -3 Spd
• Manufacturer: Lattice

Specifications of LCMXO640C-3MN100C

• Memory Type: SRAM
• Number Of Macrocells: 320
• Maximum Operating Frequency: 500 MHz
• Delay Time: 4.9 ns
• Number Of Programmable I/os: 74
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Supply Current: 17 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: CSBGA-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 1.71 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock/Control Distribution Network
The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four
primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in
Figure 2-7 and Figure 2-8. The available clock sources for the MachXO256 and MachXO640 devices are four dual
function clock pins and 12 internal routing signals. The available clock sources for the MachXO1200 and
MachXO2280 devices are four dual function clock pins, up to nine internal routing signals and up to six PLL out-
puts.
Figure 2-7. Primary Clocks for MachXO256 and MachXO640 Devices
Routing
12
Clock
Pads
4
2-7
16:1
16:1
16:1
16:1
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
MachXO Family Data Sheet
Architecture