LCMXO640C-3MN100C Lattice, LCMXO640C-3MN100C Datasheet - Page 35

• Manufacturer Part Number: LCMXO640C-3MN100C
• Description: CPLD - Complex Programmable Logic Devices 640 LUTs 74 IO 1.8/2 .5/3.3V -3 Spd
• Manufacturer: Lattice

Specifications of LCMXO640C-3MN100C

• Memory Type: SRAM
• Number Of Macrocells: 320
• Maximum Operating Frequency: 500 MHz
• Delay Time: 4.9 ns
• Number Of Programmable I/os: 74
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Supply Current: 17 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: CSBGA-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 1.71 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 3-1. LVDS DC Conditions
BLVDS
The MachXO family supports the BLVDS standard through emulation. The output is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. The input standard is
supported by the LVDS differential input buffer on certain devices. BLVDS is intended for use when multi-drop and
bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution
for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Z
R
R
R
V
V
V
V
Z
I
DC
OUT
OH
OL
OD
CM
BACK
S
P
T
Parameter
16mA
16mA
2.5V
2.5V
+
-
Output impedance
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
Back impedance
DC output current
80
80
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
Over Recommended Operating Conditions
45-90 ohms
80
16mA
Description
2.5V
80
16mA
3-9
-
. . .
. . .
2.5V
80
16mA
Typical
1.43
1.07
0.35
1.25
3.66
294
121
100
100
20
DC and Switching Characteristics
2.5V
80
45-90 ohms
16mA
MachXO Family Data Sheet
80
-
2.5V
2.5V
16mA
16mA
+
-
Units
mA
Ω
Ω
Ω
Ω
Ω
V
V
V
V