LCMXO640C-3MN100C Lattice, LCMXO640C-3MN100C Datasheet - Page 26
![CPLD - Complex Programmable Logic Devices 640 LUTs 74 IO 1.8/2 .5/3.3V -3 Spd](/photos/16/14/161487/img32096_sml.jpg)
LCMXO640C-3MN100C
Manufacturer Part Number
LCMXO640C-3MN100C
Description
CPLD - Complex Programmable Logic Devices 640 LUTs 74 IO 1.8/2 .5/3.3V -3 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO640C-3MN100C
Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
500 MHz
Delay Time
4.9 ns
Number Of Programmable I/os
74
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
17 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
CSBGA-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO640C-3MN100C
Manufacturer:
ZARLINK
Quantity:
984
Company:
Part Number:
LCMXO640C-3MN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 2-22. MachXO Configuration and Programming
Density Shifting
The MachXO family has been designed to enable density migration in the same package. Furthermore, the archi-
tecture ensures a high success rate when performing design migration from lower density parts to higher density
parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a
lower density device. However, the exact details of the final resource utilization will impact the likely success in
each case.
Port
Mode
Program in seconds
Memory Space
Non-Volatile
Background
ISP 1149.1 TAP Port
microseconds
Download in
Power-up
Refresh
2-23
SRAM Memory
Space
1532
MachXO Family Data Sheet
Configure in milliseconds
Architecture