LCMXO640C-3MN100C Lattice, LCMXO640C-3MN100C Datasheet - Page 20

CPLD - Complex Programmable Logic Devices 640 LUTs 74 IO 1.8/2 .5/3.3V -3 Spd

LCMXO640C-3MN100C

Manufacturer Part Number
LCMXO640C-3MN100C
Description
CPLD - Complex Programmable Logic Devices 640 LUTs 74 IO 1.8/2 .5/3.3V -3 Spd
Manufacturer
Lattice
Datasheet

Specifications of LCMXO640C-3MN100C

Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
500 MHz
Delay Time
4.9 ns
Number Of Programmable I/os
74
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
17 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
CSBGA-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO640C-3MN100C
Manufacturer:
ZARLINK
Quantity:
984
Part Number:
LCMXO640C-3MN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Table 2-8. I/O Support Device by Device
Table 2-9. Supported Input Standards
Number of I/O Banks
Type of Input Buffers
Types of Output Buffers
Differential Output
Emulation Capability
PCI Support
Single Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI
Differential Interfaces
BLVDS
1. Top Banks of MachXO1200 and MachXO2280 devices only.
2. MachXO1200 and MachXO2280 devices only.
2
Single-ended
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
All I/O Banks
No
1
2
MachXO256
, LVDS
Input Standard
2
, LVPECL
2
, RSDS
4
Single-ended
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
All I/O Banks
No
MachXO640
2
2-17
3.3V
2.5V
VCCIO (Typ.)
8
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
Differential buffers with
true LVDS outputs (50%
on left and right side)
All I/O Banks
Top side only
1.8V
MachXO1200
MachXO Family Data Sheet
1.5V
1.2V
8
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
Differential buffers with
true LVDS outputs (50%
on left and right side)
All I/O Banks
Top side only
MachXO2280
Architecture

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