A54SX08A-TQG100 Actel, A54SX08A-TQG100 Datasheet - Page 19

• Manufacturer Part Number: A54SX08A-TQG100
• Description: FPGA - Field Programmable Gate Array 12K System Gates
• Manufacturer: Actel

Specifications of A54SX08A-TQG100

• Processor Series: A54SX08
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 130
• Delay Time: 4 ns to 8.4 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 8000
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
CLKA/B, I/O
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL,
LVTTL, LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. The
clock input is buffered prior to clocking the R-cells. When
not used, this pin must be tied Low or High (NOT left
floating) on the board to avoid unwanted power
consumption.
For A54SX72A, these pins can also be configured as user
I/Os. When employed as user I/Os, these pins offer built-
in programmable pull-up or pull-down resistors active
during power-up only. When not used, these pins must
be tied Low or High (NOT left floating).
QCLKA/B/C/D, I/O
These four pins are the quadrant clock inputs and are
only used for A54SX72A with A, B, C, and D
corresponding to bottom-left, bottom-right, top-left,
and top-right quadrants, respectively. They are clock
inputs for clock distribution networks. Input levels are
compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V
PCI, or 5 V PCI specifications. Each of these clock inputs
can drive up to a quarter of the chip, or they can be
grouped together to drive multiple quadrants. The clock
input is buffered prior to clocking the R-cells. When not
used, these pins must be tied Low or High on the board
(NOT left floating).
These pins can also be configured as user I/Os. When
employed as user I/Os, these pins offer built-in
programmable pull-up or pull-down resistors active
during power-up only.
GND
Low supply voltage.
HCLK
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL, LVTTL,
LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. This input is
directly wired to each R-cell and offers clock speeds
independent of the number of R-cells being driven.
When not used, HCLK must be tied Low or High on the
board (NOT left floating). When used, this pin should be
held Low or High during power-up to avoid unwanted
static power consumption.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL, LVTTL, LVCMOS2, 3.3 V PCI or 5 V PCI specifications.
Unused I/O pins are automatically tristated by the
Designer software.
NC
This pin is not connected to circuitry within the device
and can be driven to any voltage or be left floating with
no effect on the operation of the device.
Clock A and B
Quadrant Clock A, B, C, and D
Ground
Dedicated (Hardwired)
Array Clock
Input/Output
No Connection
v5.3
PRA/B, I/O
The Probe pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the other
probe pin to allow real-time diagnostic output of any
signal path within the device. The Probe pin can be used
as a user-defined I/O when verification has been
completed.
permanently disabled to protect programmed design
confidentiality.
TCK, I/O
Test clock input for diagnostic probe and device
programming. In Flexible mode, TCK becomes active
when the TMS pin is set Low (refer to
page
boundary scan state machine reaches the "logic reset"
state.
TDI, I/O
Serial input for boundary scan testing and diagnostic
probe. In Flexible mode, TDI is active when the TMS pin is
set Low (refer to
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDO, I/O
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set Low (refer to
Table 1-6 on page
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer II is being used, TDO
will act as an output when the checksum command is
run. It will return to user /IO when checksum is complete.
TMS
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set Low, the TCK, TDI, and
TDO pins are boundary scan pins (refer to
page
they will remain in that mode until the internal
boundary scan state machine reaches the logic reset
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The logic
reset state is reached five TCK cycles after the TMS pin is
set High. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
TRST, I/O
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the Reserve JTAG Reset Pin is
not selected in Designer.
V
Supply voltage for I/Os. See
V
V
Supply voltage for array. See
V
CCI
CCI
CCA
CCA
power pins in the device should be connected.
power pins in the device should be connected.
1-9). This pin functions as an I/O when the
1-9). Once the boundary scan pins are in test mode,
The
Probe A/B
Test Clock
Test Data Input
Test Data Output
Test Mode Select
Boundary Scan Reset Pin
Supply Voltage
Supply Voltage
1-9). This pin functions as an I/O when
pin’s
Table 1-6 on page
probe
Table 2-2 on page
Table 2-2 on page
capabilities
SX-A Family FPGAs
1-9). This pin
Table 1-6 on
Table 1-6 on
can
2-1. All
2-1. All
1-15
be