A54SX08A-TQG100 Actel, A54SX08A-TQG100 Datasheet - Page 61
![FPGA - Field Programmable Gate Array 12K System Gates](/photos/16/14/161495/tqfp-100_sml.jpg)
A54SX08A-TQG100
Manufacturer Part Number
A54SX08A-TQG100
Description
FPGA - Field Programmable Gate Array 12K System Gates
Manufacturer
Actel
Datasheet
1.A54SX08A-TQG100.pdf
(108 pages)
Specifications of A54SX08A-TQG100
Processor Series
A54SX08
Core
IP Core
Number Of Macrocells
512
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
130
Delay Time
4 ns to 8.4 ns
Supply Voltage (max)
5.25 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
2.25 V
Number Of Gates
8000
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A54SX08A-TQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A54SX08A-TQG100
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
A54SX08A-TQG100A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A54SX08A-TQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-34 • A54SX32A Timing Characteristics
Parameter
5 V PCI Output Module Timing
t
t
t
t
t
t
d
d
5 V TTL Output Module Timing
t
t
t
t
t
t
t
t
d
d
d
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 50 pF loading.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V
4. Delays based on 35 pF loading.
DLH
DHL
ENZL
ENZH
ENLZ
ENHZ
DLH
DHL
DHLS
ENZL
ENZLS
ENZH
ENLZ
ENHZ
TLH
THL
TLH
THL
THLS
Slew Rate [V/ns] = (0.1*V
where C
3
3
3
3
3
d
load
T[LH|HL|HLS]
(Worst-Case Commercial Conditions V
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
Delta High to Low
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
Delta High to Low
Delta High to Low—low slew
is the load capacitance driven by the I/O in pF
is the worst case delta value from the datasheet in ns/pF.
Description
CCI
– 0.9*V
2
4
CCI)
/ (C
load
* d
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
–3 Speed
T[LH|HL|HLS]
CCA
= 2.25 V, V
0.016
0.026
0.014
0.023
0.043
2.1
2.8
1.3
2.1
3.0
2.8
1.9
2.5
6.6
2.1
7.4
1.9
3.6
2.5
1
)
v5.3
–2 Speed
CCI
= 4.75 V, T
0.016
0.017
0.029
0.046
0.03
2.4
3.2
1.5
2.4
3.5
3.2
2.2
2.9
7.6
2.4
8.4
2.2
4.2
2.9
–1 Speed
J
= 70°C)
0.031
0.032
0.017
0.057
0.02
2.8
3.6
1.7
2.8
3.9
3.6
2.5
3.3
8.6
2.7
9.5
2.5
4.7
3.3
CCI
Std. Speed
value into the following equation:
0.022
0.023
0.037
0.066
0.04
10.1
11.0
3.2
4.2
2.0
3.2
4.6
4.2
2.9
3.9
3.2
2.9
5.6
3.9
SX-A Family FPGAs
–F Speed
0.032 ns/pF
0.052 ns/pF
0.031 ns/pF
0.051 ns/pF
0.089 ns/pF
14.2
15.4
4.5
5.9
2.8
4.5
6.4
5.9
4.1
5.4
4.5
4.1
7.8
5.4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-41