A54SX08A-TQG100 Actel, A54SX08A-TQG100 Datasheet - Page 26

FPGA - Field Programmable Gate Array 12K System Gates

A54SX08A-TQG100

Manufacturer Part Number
A54SX08A-TQG100
Description
FPGA - Field Programmable Gate Array 12K System Gates
Manufacturer
Actel
Datasheet

Specifications of A54SX08A-TQG100

Processor Series
A54SX08
Core
IP Core
Number Of Macrocells
512
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
130
Delay Time
4 ns to 8.4 ns
Supply Voltage (max)
5.25 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
2.25 V
Number Of Gates
8000
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A54SX08A-TQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A54SX08A-TQG100
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Part Number:
A54SX08A-TQG100A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A54SX08A-TQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-10 • AC Specifications (3.3 V PCI Operation)
2 -6
Symbol
I
I
I
I
slew
slew
Notes:
1. Refer to the V/I curves in
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
OH(AC)
OL(AC)
CL
CH
SX-A Family FPGAs
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
and D) are provided with the respective diagrams in
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain
outputs.
R
F
Parameter
Switching Current High
(Test Point)
Switching Current Low
(Test Point)
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
Figure 2-2 on page
Condition
0 < V
0.3V
0.7V
V
V
0.6V
0.18V
V
–3 < V
V
0.2V
0.6V
OUT
CCI
OUT
CCI
2-7. Switching current characteristics for REQ# and GNT# are permitted to be one half
CCI
CCI
CCI
CCI
CCI
> V
+ 4 > V
OUT
= 0.7V
= 0.18V
CCI
IN
Output
Buffer
Output
Buffer
≤ V
< V
> V
- 0.6V
- 0.2V
OUT
≤ –1
≤ 0.3V
> V
OUT
OUT
OUT
1 k/25 Ω
CC
IN
≥ 0.6V
OUT
Figure 2-2 on page
Pin
CC
Pin
CCI
CCI
≥ V
2
< 0.9V
< V
> 0.1V
CCI
2
> 0
load
load
CCI
CCI
CCI
1
v5.3
1, 2
+ 1
10 pF
CCI
CCI
1
3
3
1, 2
1/2 in. max.
1
1
10 pF
1 k/25 Ω
2-7. The equation defined maximum should be met by
25 + (V
–25 + (V
(–17.1(V
IN
(26.7V
–12V
– V
16V
Min.
IN
CCI
1
1
CCI
+ 1)/0.015
CCI
CCI
OUT
– V
– 1)/0.015
)
OUT
))
EQ 2-3 on
EQ 2-4 on
page 2-7
page 2-7
–32V
38V
Max.
4
4
CCI
CCI
Units
V/ns
V/ns
mA
mA
mA
mA
mA
mA
mA
mA

Related parts for A54SX08A-TQG100