LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 204

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Appendix A. Attribute Definitions
DATA_WIDTH
Data width is associated with the RAM and FIFO elements. The DATA_WIDTH attribute will define the number of
bits in each word. It takes the values as defined in the RAM size tables in each memory module.
REGMODE
REGMODE or the Register mode attribute is used to enable pipelining in the memory. This attribute is associated
with the RAM and FIFO elements. The REGMODE attribute takes the NOREG or OUTREG mode parameter that
disables and enables the output pipeline registers.
RESETMODE
The RESETMODE attribute allows users to select the mode of reset in the memory. This attribute is associated
with the block RAM elements. RESETMODE takes two parameters: SYNC and ASYNC. SYNC means that the
memory reset is synchronized with the clock. ASYNC means that the memory reset is asynchronous to clock.
CSDECODE
CSDECODE or the Chip Select Decode attributes are associated to block RAM elements. CS, or Chip Select, is
the port available in the EBR primitive that is useful when memory requires multiple EBR blocks cascaded. The CS
signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit bus, so it can cascade
eight memories easily. CSDECODE takes the following parameters: “000”, “001”, “010”, “011”, “100”, “101”, “110”,
and “111”. CSDECODE values determine the decoding value of CS[2:0]. CSDECODE_W is chip select decode for
write and CSDECODE_R is chip select decode for read for Pseudo Dual Port RAM. CSDECODE_A and
CSDECODE_B are used for true dual port RAM elements and refer to the A and B ports.
WRITEMODE
The WRITEMODE attribute is associated with the block RAM elements. It takes the NORMAL, WRITETHROUGH,
and READBEFOREWRITE mode parameters.
In NORMAL mode, the output data does not change or get updated, during the write operation. This mode is sup-
ported for all data widths.
In WRITETHROUGH mode, the output data is updated with the input data during the write cycle. This mode is sup-
ported for all data widths.
In READBEFOREWRITE mode, the output data port is updated with the existing data stored in the write address,
during a write cycle. This mode is supported for x9, x18 and x36 data widths.
WRITEMODE_A and WRITEMODE_B are used for dual port RAM elements and refer to the A and B ports in case
of a True Dual Port RAM.
For all modes (of the True Dual Port module), simultaneous read access from one port and write access from the
other port to the same memory address is not recommended. The read data may be unknown in this situation.
Also, simultaneous write access to the same address from both ports is not recommended. (When this occurs, the
data stored in the address becomes undetermined when one port tries to write a ‘H’ and the other tries to write a
‘L’).
It is recommended that the designer implements control logic to identify this situation if it occurs and either:
GSR
GSR or the Global Set/ Reset attribute is used to enable or disable the global set/reset for RAM element.
1. Implement status signals to flag the read data as possibly invalid, or
2. Implement control logic to prevent the simultaneous access from both ports.
10-54
LatticeXP2 Memory Usage Guide