LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 266

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice XP2 sysDSP Usage Guide
MULTADDSUBSUM Module
The MULTADDSUBSUM GUI configures Multiplier Addition/Subtraction Addition elements to be packed into the
primitives MULT18X18ADDSUBSUMB or MULT9X9ADDSUBSUMB. The Basic mode, shown in Figure 13-8, con-
sists of an optional one clock, one clock enable and one reset tied to all registers. Multiple sysDSP Blocks can be
spanned to accommodate large multiplications. If sysDSP blocks are spanned, additional LUT logic may be
required. Select Area/Speed to determine the LUT implementation. The input data format can be selected as Par-
allel, Shift or Dynamic. The Shift format is can only be enabled if inputs are less than 18 bits. The Shift format
enables a sample/shift register, which is useful in applications such as the FIR filter. The Advanced mode, shown in
Figure 13-9, provides finer control over the registers. In the advanced mode, users can control each register with
independent clocks, clock enables and resets. MULTADDSUBSUM inputs can be from 2 to 72 bits.
Figure 13-8. MULTADDSUBSUM Mode Basic Set-up
13-7