LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 7

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 High-Speed I/O Interface
Basic Specifications for TAG Memory............................................................................................................ 10-41
Initializing Memory ......................................................................................................................................... 10-50
FlashBak™ Capability.................................................................................................................................... 10-52
Technical Support Assistance........................................................................................................................ 10-52
Revision History ............................................................................................................................................. 10-53
Appendix A. Attribute Definitions.................................................................................................................... 10-54
Introduction ...................................................................................................................................................... 11-1
DDR and DDR2 SDRAM Interfaces Overview................................................................................................. 11-1
Implementing DDR Memory Interfaces with LatticeXP2 Devices .................................................................... 11-3
Memory Read Implementation ....................................................................................................................... 11-14
Generic High Speed DDR Implementation .................................................................................................... 11-22
DDR Usage In IPexpress ............................................................................................................................... 11-34
FCRAM (“Fast Cycle Random Access Memory”) Interface ........................................................................... 11-39
Board Design Guidelines ............................................................................................................................... 11-39
References..................................................................................................................................................... 11-39
Technical Support Assistance........................................................................................................................ 11-40
Revision History ............................................................................................................................................. 11-40
Pseudo Dual Port RAM (RAM_DP) – EBR Based ................................................................................ 10-17
Read Only Memory (ROM) - EBR Based.............................................................................................. 10-20
First In First Out (FIFO, FIFO_DC) – EBR Based................................................................................. 10-23
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based........................................................ 10-35
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based .......................................................... 10-37
Distributed ROM (Distributed_ROM) – PFU Based .............................................................................. 10-39
User TAG Memory ................................................................................................................................ 10-41
General Description .............................................................................................................................. 10-43
Pin Descriptions .................................................................................................................................... 10-43
SPI Operations...................................................................................................................................... 10-44
Specifications and Timing Diagrams..................................................................................................... 10-49
Initialization File Format ........................................................................................................................ 10-50
Binary File ............................................................................................................................................. 10-51
Hex File ................................................................................................................................................. 10-51
Addressed Hex...................................................................................................................................... 10-51
DATA_WIDTH....................................................................................................................................... 10-54
REGMODE............................................................................................................................................ 10-54
RESETMODE ....................................................................................................................................... 10-54
CSDECODE.......................................................................................................................................... 10-54
WRITEMODE........................................................................................................................................ 10-54
GSR ...................................................................................................................................................... 10-54
DQS Grouping......................................................................................................................................... 11-3
DDR Software Primitives......................................................................................................................... 11-4
DLL Compensated DQS Delay Elements ............................................................................................. 11-14
DQS Transition Detect or Automatic Clock Polarity Select ................................................................... 11-14
Data Valid Module................................................................................................................................. 11-15
DDR I/O Register Implementation......................................................................................................... 11-15
Memory Read Implementation in Software ........................................................................................... 11-15
Read Timing Waveforms....................................................................................................................... 11-16
Memory Write Implementation .............................................................................................................. 11-19
Generic DDR Software Primitives ......................................................................................................... 11-23
Design Rules/Guidelines....................................................................................................................... 11-34
DDR Generic......................................................................................................................................... 11-35
Configuration Tab.................................................................................................................................. 11-36
DDR_MEM ............................................................................................................................................ 11-36
Configuration Tab.................................................................................................................................. 11-37
6
LatticeXP2 Family Handbook
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