LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 227

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The data going to the DDR registers can be optionally delayed before going to the DDR register block.
Generic DDR Software Primitives
The IPexpress tool in the ispLEVER software can be used to generate the DDR modules. The various DDR modes
described below can be configured in the IPexpress tool. The various modes are implemented using the following
software primitives.
• IDDRXC – DDR Generic Input
• IDDRFXA – DDR Generic Input with full clock transfer (x1 gearbox)
• IDDRX2B – DDR Generic Input with 2x gearing ratio. DDRX2 inputs a double data rate signal as four data
• ODDRXC – DDR Generic Output
• ODDRX2B – DDR Generic Output with 2x gearing ratio. The DDRX2 inputs four separate data streams and out-
• DELAYB – The DDR input can be optionally delayed before it is input to the DDR registers. The user can choose
IDDRXC
This primitive inputs DDR data at both edges of the CLK and generates two streams of data. The CLK to this mod-
ule can be connected to either the edge clock or the primary FPGA clock.
Figure 11-26 shows the primitive symbol for IDDRXC mode.
Figure 11-26. IDDRXC Symbol
Table 11-6 lists the port names and descriptions for the IDDRXC primitive.
Table 11-6. IDDRXC Port Names
Figure 11-27 shows the LatticeXP2 Input Register Block configured in the IDDRXFC mode.
streams. Two stages of DDR registers are used to convert serial DDR data at input pad into four SDR data
streams entering FPGA core logic.
puts a single data stream to the I/O buffer.
to implement a fixed delay value or use a dynamic delay.
D
CLK
CE
RST
QA
QB
Port Name
I/O
O
O
I
I
I
I
DDR data
This clock can be connected to the ECLK or the FPGA clock
Clock enable signal
Reset to the DDR register
Data at the positive edge of the clock
Data at the negative edge of the clock
D
CLK
CE
RST
IDDRXC
11-23
QA
QB
Definition
LatticeXP2 High-Speed I/O Interface