LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 291

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 sysCONFIG Usage Guide
Configuration Modes and Options
The LatticeXP2 device supports two configuration modes, utilizing the SPI port or self-configuration. On power up,
or upon driving the PROGRAMN pin low depending upon the current mode, the CFG[1:0] pins are sampled to
determine the mode that will be used to configure the LatticeXP2 device. The CFG pins are generally hard wired on
the PCB and determine how the device will retrieve its configuration data. The SLAVE_SPI_PORT preference is a
programmable option which can be set using the Design Planner in Lattice ispLEVER design software, or as HDL
source file attributes, and allow the user to protect the configuration pins from accidental use by the user or the
place-and-route software.
Configuration Options
Several configuration options are available for each configuration mode.
• When using a master clock, the master clock frequency can be set.
• A security bit is provided to prevent SRAM or Flash readback.
By setting the proper parameters in the Lattice ispLEVER design software the selected configuration options are
set in the generated bitstream. As the bitstream is loaded into the device the selected configuration options take
effect. These options are described in the following sections.
Master Clock
If the LatticeXP2 is a Master device the CCLK pin will become an output with the frequency set by the user. The
default Master Clock Frequency is 2.5 MHz. The software default adjusts the MCLK frequency to 3.1 MHz in the
programming bitstream.
The user can determine the Master Clock frequency by setting the MCCLK_FREQ. One of the first things loaded
during configuration is the MCCLK_FREQ parameter; once this parameter is loaded the frequency changes to the
selected value using a glitchless switch. Care should be exercised not to exceed the frequency specification of the
slave devices or the signal integrity capabilities of the PCB layout.
The MCCLK frequency selections made by the user are only valid if the LatticeXP2 device is booted from external
SPI Flash. The internal Flash will not control the MCCLK frequency setting in the JEDEC file. In the case of device
boot from internal Flash the MCCLK frequency is always 3.1 MHz. In the case of booting the device from external
SPI Flash, the user can use UFW program inside the ispVM tool suite to convert the JEDEC file to bitstream for-
mat. The UFW program supports MCCLK_FREQ selections. In this case the user can select MCCLK_FREQ dur-
ing bitstream conversion. MCCLK FREQ selections from UFW range 2.5 MHz to 130 MHz.
Security Bit
Setting the security bit prevents readback of the SRAM and Flash from JTAG or the sysCONFIG pins. When the
security bit is set the only operations available are erase and write. The security bit is updated as the last operation
of SRAM configuration or Flash programming. By using on-chip Flash, and setting the security bit, the user can
create a very secure device.
The security bit is accessed via the Design Planner in ispLEVER design software.
More information on device security can be found in the document
FPGA Design Security Issues: Using the
ispXPGA Family of FPGAs to Achieve High Design
Security.
Slave SPI Mode
In the Slave SPI mode the CCLK pin becomes an input and commands will be read into the LatticeXP2 on the
SISPI pin at the rising edge of CCLK. Data will be written out of the LatticeXP2 on the SOSPI pin at the falling edge
of CCLK.
Care must be exercised during read back of EBR or PFU memory. It is up to the user to ensure that reading these
RAMs will not cause data corruption, i.e. these RAMs may not be read while being accessed by user code.
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