LFXP2-8E-5TN144I Lattice, LFXP2-8E-5TN144I Datasheet - Page 288

• Manufacturer Part Number: LFXP2-8E-5TN144I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5TN144I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 100
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 14-3. Flash Programming Mode Pin Usage
Table 14-4. Memory Access Modes
External SPI Flash
When the Master SPI mode is used for configuration an external SPI Flash device is required to hold the configura-
tion data. The size of the bitstream and the required external SPI Flash is shown in Table 14-5.
Table 14-5. Maximum Configuration Bits
PROGRAMN
INITN
DONE
SLAVE_SPI_PORT preference
1. ispJTAG can be used to program the Flash regardless of the state of the CFG pins.
2. The state of the PROGRAMN pin is ignored by the device during JTAG Flash programming but the pin should be held high as a low will
3. The state of the INITN pin is ignored by the device during JTAG Flash programming but the pin should be allowed to float high using the
4. The state of the DONE pin is ignored by the device during JTAG Flash programming but the pin should be allowed to float high using the
5. The SLAVE_SPI_PORT preference must be set to ENABLE to use the Slave SPI port after the device has been configured. The Slave SPI
6. The Master SPI port can only be used to configure the SRAM in direct mode from an external SPI Flash memory. The CFG pins must be
cause a configuration failure. When the device is in the SDM mode, the PROGRAMN pin is a dedicated I/O pin so it does not affect config-
uration.
internal pull-up. When the device is in the SDM mode, the INITN pin is a dedicated I/O pin so it does not affect configuration.
internal pull-up as a low can keep the device from waking up. When the device is in the SDM mode, the DONE pin is a dedicated I/O pin so
it does not affect configuration.
port is also available when the device is not configured.
set per Table 14-2 to enable this mode.
Flash Programming Mode
User I/O States
Port
Pins
1. Slave SPI mode can only write to on-chip Flash memory in background mode unless the Flash
2. Slave SPI mode can read from on-chip Flash memory in background mode only.
3. Master SPI mode can write to SRAM in direct mode only.
memory is erased.
Master SPI
Slave SPI
6
Mode
Density
XP2-17
XP2-30
XP2-40
XP2-5
XP2-8
Read
CCLK, CSSPISN, SISPI, SOSPI
Yes
No
Don’t Care
Pass/Fail
Tristate
2
Direct
Done

Flash
Bitstream Size (Mb)
Slave SPI
t5
Write
14-6
Yes
1.27
1.99
3.54
5.79
8.03
Background
No
Keep at High
ENABLE
Not Used
Pass/Fail
1
User
5
LatticeXP2 sysCONFIG Usage Guide
Read
Yes
No
SPI Flash (Mb)
BSCAN
Direct
SRAM
16
2
2
4
8
Keep At High
Keep at High
Don’t Care
Write
Not Used
ispJTAG
Yes
No
TAP
3
1
3
Background
4
2
User