A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 12

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A3PE1500-FGG676

Manufacturer Part Number
A3PE1500-FGG676
Description
FPGA - Field Programmable Gate Array 1500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A3PE1500-FGG676

Processor Series
A3PE1500
Core
IP Core
Maximum Operating Frequency
231 MHz
Number Of Programmable I/os
444
Data Ram Size
276480
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1.5 M
Package / Case
FPBGA-676
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ProASIC3E Device Family Overview
1 - 6
Pro I/Os with Advanced I/O Standards
The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-ended,
differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two
per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is
subdivided into V
18 I/Os. All the I/Os in a given minibank share a common V
minibank is configured as a V
reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
ProASIC3E banks support M-LVDS with 20 multi-drop points.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)
REF
minibanks, which are used by voltage-referenced I/Os. V
REF
pin, the remaining I/Os in that minibank will be able to use that
R e vi s i o n 9
REF
line. Therefore, if any I/O in a given V
REF
minibanks contain 8 to
REF

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