A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 45

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A3PE1500-FGG676

Manufacturer Part Number
A3PE1500-FGG676
Description
FPGA - Field Programmable Gate Array 1500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A3PE1500-FGG676

Processor Series
A3PE1500
Core
IP Core
Maximum Operating Frequency
231 MHz
Number Of Programmable I/os
444
Data Ram Size
276480
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1.5 M
Package / Case
FPBGA-676
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
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A3PE1500-FGG676
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Part Number:
A3PE1500-FGG676
Manufacturer:
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Part Number:
A3PE1500-FGG676I
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Table 2-37 • Minimum and Maximum DC Input and Output Levels
Figure 2-8 • AC Loading
Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads
1.8 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = V
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
1.8 V LVCMOS
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
V
Test Point
Datapath
VIL
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
Max.
trip
V
. See
Input High (V)
Table 2-15 on page 2-19
1.8
35 pF
Min.
V
VIH
Max.
Enable Path
3.6
3.6
3.6
3.6
3.6
3.6
Test Point
Measuring Point* (V)
V
R = 1 k
Max.
VOL
0.45
0.45
0.45
0.45
0.45
0.45
for a complete table of trip points.
V
0.9
R e v i s i o n 9
VCCI – 0.45 2
VCCI – 0.45 4
VCCI – 0.45 6
VCCI – 0.45 8
VCCI – 0.45 12 12
VCCI – 0.45 16 16
VOH
Min.
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
V
V
mA mA
I
OL
REF
HZ
ZH
I
/ t
OH
(typ.) (V)
2
4
6
8
/ t
LZ
HZ
LZ
ZHS
/ t
/ t
Max.
mA
I
ZL
ZH
OSL
22
44
51
74
/ t
11
74
ProASIC3E Flash Family FPGAs
ZL
/ t
3
/ t
ZLS
ZHS
/ t
ZLS
Max.
I
mA
C
OSH
17
35
45
91
91
9
LOAD
3
35
(pF)
µA
I
10 10
10 10
10 10
10 10
10 10
10 10
IL
1
4
µA
I
2- 33
IH
2
4

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