A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 37

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-25 • Minimum and Maximum DC Input and Output Levels
Table 2-26 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
4 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
3.3 V
LVCMOS
Wide
Range
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
2. I
3. I
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
larger when operating outside recommended ranges.
operate at the equivalent software default drive strength. These values are for normal ranges ONLY.
larger when operating outside recommended ranges.
IL
IH
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
Equivalent
Software
Default
Drive
Strength
Option
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is
supported as part of the 3.3 V LVTTL support.
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
1
V
VIL
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Max.
V
0.8
0.8
0.8
0.8
0.8
V
VIL
Max.
0.8
0.8
0.8
0.8
0.8
0.8
0.8
V
Min.,
V
2
2
2
2
2
VIH
Min.
V
2
2
2
2
2
2
2
Max.
3.6
3.6
3.6
3.6
3.6
V
VIH
Max.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
Max.
VOL
0.4
0.4
0.4
0.4
0.4
V
R e v i s i o n 9
Max.
VOL
0.2
0.2
0.2
0.2
0.2
0.2
0.2
V
VOH
Min.
2.4
2.4
2.4
2.4
2.4
V
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VDD – 0.2 100 100
VOH
Min.
mA mA
I
V
12 12
16 16
24 24
OL
4
8
I
OH
4
8
I
µA µA
OL
I
OH
Max.
mA
I
109
127
181
OSL
27
54
ProASIC3E Flash Family FPGAs
3
Max.
mA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
I
OSL
4
Max.
I
mA
103
132
268
OSH
25
51
Max.
mA
I
TBD
TBD
TBD
TBD
TBD
TBD
TBD
OSH
3
4
µA
µA
I
I
10
10
10
10
10
10
10
10
10
10
10
10
IL
IL
2
1
4
5
µA
µA
I
I
10
10
10
10
10
10
10
2- 25
10
10
10
10
10
IH
IH
2
3
4
5