A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 80

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3E DC and Switching Characteristics
Global Resource Characteristics
Figure 2-37 • Example of Global Tree Use in an A3PE600 Device for Clock Routing
2- 68
CCC
A3PE600 Clock Tree Topology
Clock delays are device-specific.
global tree presented in
It is used to drive all D-flip-flops in the device.
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the
page
device. Minimum and maximum delays are measured with minimum and maximum loading.
2-69, and
"Clock Conditioning Circuits" section on page
Table 2-97 on page 2-70
Figure 2-37
Figure 2-37
is driven by a CCC located on the west side of the A3PE600 device.
present minimum and maximum global clock delays within the
R e visio n 9
is an example of a global tree used for clock routing. The
2-71.
Table 2-95 on page
2-69,
Table 2-96 on
Central
Global Rib
VersaTile
Rows
Global Spine