A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 64

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3E DC and Switching Characteristics
Figure 2-23 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-81 • Minimum and Maximum DC Input and Output Levels
Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-83 • LVPECL
2- 52
DC Parameter
VCCI
VOL
VOH
VIL, VIH
V
V
V
V
Input Low (V)
1.64
*
Speed Grade
Std.
–1
–2
Note:
OUTBUF_LVPECL
ODIFF
OCM
ICM
IDIFF
Measuring point = V
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Timing Characteristics
Supply Voltage
Output Low Voltage
Output High Voltage
Input Low, Input High Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
FPGA
trip
. See
Table 2-15 on page 2-19
Description
N
P
Input High (V)
Bourns Part Number: CAT16-PC4F12
100 Ω
100 Ω
1.94
t
0.66
0.56
0.49
DOUT
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
187 W
for a complete table of trip points.
R e visio n 9
Z
Z
1.83
1.55
1.36
t
0.625
1.762
0
0
Min.
0.96
1.01
DP
Measuring Point* (V)
300
1.8
= 50 Ω
= 50 Ω
0
3.0
Cross point
Max.
0.97
1.27
2.11
1.98
2.57
3.3
100 Ω
Table 2-6 on page 2-5
0.04
0.04
0.03
t
DIN
0.625
1.762
Min.
1.06
1.92
1.01
300
0
N
P
3.3
Max.
1.43
2.28
0.97
1.98
2.57
3.6
FPGA
1.63
1.39
1.22
+
t
–
PY
0.625
1.762
Min.
VREF (typ.) (V)
1.30
2.13
1.01
300
0
for derating values.
INBUF_LVPECL
3.6
Figure
–
Max.
1.57
2.41
0.97
1.98
2.57
3.9
Units
ns
ns
ns
2-23. The
Units
mV
V
V
V
V
V
V
V