A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 8

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3E Device Family Overview
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Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3E FPGAs
do not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Live at Power-Up
The Actel flash-based ProASIC3E devices support Level 0 of the LAPU classification standard. This
feature helps in system component initialization, execution of critical tasks before the processor wakes
up, setup and configuration of memory blocks, clock generation, and bus activity management. The
LAPU feature of flash-based ProASIC3E devices greatly simplifies total system design and reduces total
system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these
purposes in a system. In addition, glitches and brownouts in system power will not corrupt the
ProASIC3E device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be
reloaded when system power is restored. This enables the reduction or complete removal of the
configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from
the PCB design. Flash-based ProASIC3E devices simplify total system design and reduce cost and
design risk while increasing system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3E flash-based
FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3E FPGAs cannot be
altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3E devices exhibit power characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3E devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3E devices also have low dynamic power consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3E family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
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