A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 53

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-54 • Minimum and Maximum DC Input and Output Levels
Figure 2-13 • AC Loading
Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-56 • 3.3 V GTL+
3.3 V GTL+
Drive
Strength
35 mA
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.1
*
Speed
Grade
Std.
–1
–2
Note:
Measuring point = Vtrip. See
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Worst-Case V
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The V
Timing Characteristics
Min.
–0.3
t
V
DOUT
0.60
0.51
0.45
VREF – 0.1 VREF + 0.1
VIL
Input High (V)
VREF + 0.1
Max.
2.06
1.75
1.53
V
t
DP
C
CI = 3.0 V, VREF = 1.0 V
Table 2-15 on page 2-19
0.04
0.04
0.03
t
DIN
Min.
V
VIH
1.59
1.35
1.19
Measuring
t
Point* (V)
PY
Test Point
J
1.0
Max.
= 70°C, Worst-Case VCC = 1.425 V,
3.6
V
t
0.43
0.36
0.32
EOUT
GTL+
for a complete table of trip points.
Max.
R e v i s i o n 9
VOL
0.6
V
VREF (typ.) (V)
V
2.09
1.78
1.56
t
TT
ZL
25
10 pF
VOH
1.0
Min.
V
–
2.06
1.75
1.53
t
ZH
CCI
Table 2-6 on page 2-5
mA mA
I
35 35
OL
pin should be connected to 3.3 V.
t
I
LZ
OH
VTT (typ.) (V)
t
HZ
1.5
Max.
mA
I
181
OSL
ProASIC3E Flash Family FPGAs
1
4.33
3.68
3.23
t
ZLS
for derating values.
Max.
mA
I
268
OSH
t
4.29
3.65
3.20
ZHS
C
1
LOAD
10
µA
10
I
(pF)
Units
IL
2
ns
ns
ns
µA
2- 41
I
10
IH
2