XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 55

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
R
Table 5-5: Block Erase (0x50) Command
•
•
Table 5-6: Block Addressing Summary
Notes:
1. Note: The Block Erase command is not supported in simulation.
XC3S1400AN
MOSI
XC3S200AN
XC3S400AN
XC3S700AN
XC3S50AN
Pin
Similarly, serially clock in a 24-bit block address.
♦
♦
♦
♦
Drive CSB High on the falling edge of CLK to end the command.
FPGA
Only the block address is required.
-
The number of blocks and the alignment of the block address within the 24-bit
address field varies by Spartan-3AN FPGA type, as shown in
If using the default address scheme, see
If using power-of-2 addressing, see
Command
Byte 1
0x50
The block address is always aligned to every 8 pages. It does not span across
just any block of eight contiguous pages.
Blocks
Total
256
512
512
64
Default Addressing: See
Optional Power-of-2 Addressing: See
Table A-5, page 90
High Address
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Byte 2
Block Size
(4K+128)
(2K+64)
(Bytes)
2,112
4,224
Block Address
Default
Every 4K bytes
Every 8K bytes
Table A-5, page 90
Every 8 pages
Every 8 pages
Middle Address
Alignment
Table 5-7
24-bit Address
Table 5-7
Addressing Mode
Byte 3
.
Block Size
.
(Bytes)
2,048
4,096
(2K)
(4K)
Byte Address Unused
Power-of-2
Low Address
Table
Don’t Care
Byte 4
Every 2K bytes
Every 4K bytes
XX
Every 8 pages
Every 8 pages
5-6.
Alignment
Block Erase
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