XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 85

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XC3S400AN-4FTG256I

Manufacturer Part Number
XC3S400AN-4FTG256I
Description
IC FPGA SPARTAN-3AN 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Total Ram Bits
368640
Number Of I /o
195
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Security Register Read
Table 9-3: Security Register Read Command Sequence
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
Notes:
1. The Security Register Read command is supported in simulation.
MOSI
MISO
Pin
Byte 1
0x77
Four-byte Command Sequence
R
Byte 2
XX
To read the
using the SPI_ACCESS design primitive.
High
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the four-byte Security Register Read
command sequence shown in
byte first. The last 3 bytes are dummy bytes.
After clocking in the last bit of the command sequence, receive the Security Register
data on the MISO pin
After clocking in the last data bit to program the register, drive the CSB pin High on
the falling edge of CLK.
Byte 3
XX
Receive each byte location serially, most-significant bit first.
The FPGA application can read less than the complete 128 bytes. For example, the
application can stop after reading first few bytes of the User-Defined Field.
Any data beyond the end of the 128-byte Security Register is undefined.
Security
Byte 4
XX
Register, the FPGA application must perform the following actions
Byte 5
Data 0
www.xilinx.com
XX
User-Defined Field
Byte 6
Data 1
Table 9-3
XX
... Byte 68 Byte 69 Byte 70 ... Byte 132
...
...
on the MOSI pin, most-significant bit of each
Data 63
Security Register
XX
Data 64
XX
Unique Identifier
Security Register Read
Data 65
XX
...
...
Data 127
XX
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