XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 84

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 9: Security Register
84
To issue the Security Register Program command sequence, the FPGA application must
perform the following actions using the SPI_ACCESS design primitive.
•
•
Table 9-2: Security Register Program Command Sequence
•
•
A Low-to-High transition on the CSB input completes the command sequence. The
programming operation is internally self-timed and completes in the Page Programming
time, T
During this time, the
the Security Register Program operation is in progress or whether it has completed.
MOSI
Notes:
1. The Security Register Program command is supported in simulation. The simulation model has a
Pin
default Factory ID of 00. For simulation purposes, a user parameter can set the Factory ID to a different
value (see
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the four-byte Security Register Program
command sequence shown in
byte first.
After clocking in the last bit of the command sequence, send the Security Register
programming data on the MOSI pin
♦
♦
♦
♦
After clocking in the last data bit to program the register, drive the CSB pin High on
the falling edge of CLK.
Caution!
then the content of the 64-byte User-Defined Field within the Security Register is not
guaranteed.
Caution!
values for any unspecified byte locations are not guaranteed. For example, if only the first two
bytes are clocked in rather than the complete 64 bytes, then the remaining 62 bytes of the User-
Defined Field within the Security Register are not guaranteed.
Caution!
Consequently, it is not possible to program only the first two bytes of the register and then later
program the remaining 62 bytes.
Caution!
temporary data storage. Consequently, this command overwrites any previous contents of
Buffer 1.
PP
Specify all 64 bytes.
The content of any unwritten locations is not guaranteed.
If more than 64 bytes are provided, then the additional data wraps around
starting again at location 0.
Specify each byte location serially, most-significant bit first.
Byte 1
, shown in
0x9B
Four-byte Command Sequence
Table
If the FPGA V
If less than 64 bytes of data is clocked in before the CSB pin is deasserted, then the
The User-Defined Field within the Security Register can only be programmed once.
The Security Register Program command uses the SRAM page Buffer 1 for
1-3).
Byte 2
0x00
Table 4-5, page 44
READY/BUSY
www.xilinx.com
CCAUX
Byte 3
0x00
power supply is interrupted before the erase cycle completes,
Table 9-2
Byte 4
bit (bit 7) of the
0x00
and specified in the
Spartan-3AN FPGA In-System Flash User Guide
on the MOSI pin, most-significant bit of each
User-Field
Byte 5
Data
Security Register
0
(64-byte User-Defined Field)
Security Register Value
Spartan-3AN FPGA data
User-Field
UG333 (v2.1) January 15, 2009
Byte 6
Data
1
indicates whether
...
...
User-Field
Data
Byte68
sheet.
63
R