XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 77

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
R
Unprotecting Sectors While Sector Protection Enabled
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A Low-to-High transition on the CSB input completes the command sequence and the ISF
memory then programs the Sector Protection Register. The erase operation is internally
self-timed and completes in the Page Programming time, T
shown in
this time, the
Protection Register Program operation is in progress or whether it has completed.
If the FPGA V
completes, then the content of the
The FPGA application can always erase and program the Sector Protection Register
regardless of the sector protection status.
Reprogramming the Sector Protection Register while sector protection is enabled allows
the FPGA application to temporarily unprotect an individual sector or sectors rather than
disabling the sector protection mechanism completely. However, there are limitations to
this technique as described below.
♦
♦
After clocking in the last data bit to program the register, drive the CSB pin High on
the falling edge of CLK to end the command.
Caution!
buffer. Any data stored in Buffer 1 prior to issuing the Sector Protection Register Program
command is destroyed.
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Sector 0 is subdivided into two smaller sectors, called Sector 0a and Sector 0b. See
Table 8-4, page 75
locations.
All sectors, other than Sector 0, use the same command byte, as shown in
Table 8-3, page
-
-
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Table 4-5, page 44
The first data byte corresponds to Sector 0, the second data byte to Sector 1,
and so on.
The XC3S50AN FPGA requires four bytes.
The XC3S200AN and the XC3S400AN FPGAs each require 8 bytes.
The XC3S700AN and the XC3S1400AN FPGAs require 16 bytes.
If the proper number of data bytes is not clocked in before the CSB pin is
deasserted, then the protection status of the sectors corresponding to the
unwritten bytes is not guaranteed. For example, if the FPGA application only
writes two bytes, then the protection status for the subsequent sectors is not
guaranteed.
If the FPGA application writes more than required number of bytes to the
Sector Protection Register, then the data wraps back around to the beginning
of the register. For example, if the application writes five bytes to the
XC3S50AN, then the fifth byte actually overwrites the value for Sector 0.
Write 0x00 to unprotect a sector.
Write 0xFF to protect a sector.
If a value other than 0x00 or 0xFF is clocked into the Sector Protection
Register, then the protection status of the corresponding sector is not
guaranteed.
READY/BUSY
CCAUX
The Sector Protection Register Program command uses the Buffer 1 SRAM page
power supply is interrupted before the programming operation
75.
www.xilinx.com
for information on how to protect or unprotect Sector 0
and specified in the
bit (bit 7) of the
Sector Protection Register
Status Register
Spartan-3AN FPGA data sheet.
PP
is not guaranteed.
indicates whether the Sector
, or between 4 to 6 ms as
Sector Protection
During
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