XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 65

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
Compare
ISF Memory Size
Sector Protect
R
The result of the most recent Page to Buffer Compare command is indicated by bit 6 in the
Status
Table 6-3: COMPARE
The
Table
ID information, shown in
Table 6-4: ISF Memory Size
Bit 1 in the
disabled, as defined in
Sector Protection Register
Table 6-5: SECTOR PROTECT
The Sector Protect bit does not indicate whether any sectors are locked down. To determine
if any sectors are locked down, issue a
COMPARE
PROTECT
Status Register
5
0
0
1
1
SECTOR
6-4. This memory density code is different from the code used in the JEDEC device
Register, as defined in
0
1
0
1
Status Register Bits
Status Register
4
0
1
0
0
The data stored in the ISF memory page specified by the most-recent
to Buffer Compare (Program Verify)
the specified SRAM page buffer.
One or more bits differ between the data stored in the ISF memory page
and the SRAM page buffer specified by the most-recent
Compare (Program Verify)
All memory locations open for program and erase commands.
All programming and erase commands are prevented to ISF memory
locations within the Sectors defined in the
bits 5:2 indicate the size of the ISF memory array, as defined in
Table
(Status Register
3
1
1
0
1
www.xilinx.com
Table 6-11, page
are protected against all programming and erase operations.
indicates whether Sector Protection is presently enabled or
6-5. When enabled, the designated sectors specified in the
Table
(Status Register
(Status Register
2
1
1
1
1
6-3.
Sector Lockdown Register Read
Bit 6)
69.
command.
Memory Size
Description
Description
16 Mbit
Bits 5, 4, 3, and 2)
1 Mbit
4 Mbit
8 Mbit
Bit 1)
command matches the data stored in
Sector Protection
Associated FPGA(s)
XC3S1400AN
XC3S200AN
XC3S400AN
XC3S700AN
command.
XC3S50AN
Page to Buffer
Status Register
Register.
Page
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