F276-CEG-T-TR STMicroelectronics, F276-CEG-T-TR Datasheet - Page 180

• Manufacturer Part Number: F276-CEG-T-TR
• Description: IC MCU 16BIT 832KB FLASH 144LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F276-CEG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 48MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LFQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Interface Type: CAN, I2C
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical characteristics
6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected if they are used
7. The maximum current may be drawn while the respective signal line remains inactive.
8. The minimum current must be drawn in order to drive the respective signal line active.
9. The power supply current is a function of the operating frequency (f
10. The power supply current is a function of the operating frequency (f
11. The Idle mode supply current is a function of the operating frequency (f
12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 to 0.1V or at V
180/231
for CS output and the open drain function is not enabled.
illustrated in
disconnected and all inputs at V
doing the following:
- Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): No output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
illustrated in
disconnected and all inputs at V
doing the following:
- Fetching code from all sectors of both IFlash and XFlash, accessing in read (few fetches) and write to XRAM
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channels of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): No output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
illustrated in
all inputs at V
0.1V to V
Regulator is assumed off: In case it is not, additional 1mA shall be assumed.
DD
, V
Figure 44. Port2 test mode structure
Figure 45
Figure 45
Figure 44
IL
AREF
or V
IH
= 0V, all outputs (including pins configured as outputs) disconnected. Furthermore, the Main Voltage
, RSTIN pin at V
below. This parameter is tested at V
below. This parameter is tested at V
below. These parameters are tested and at maximum CPU clock with all outputs disconnected and
IL
IL
or V
or V
Fast External Interrupt Input
IH
IH
IH1min
For Port2 complete structure refer also to
, RSTIN pin at V
, RSTIN pin at V
Flash Sense Amplifier
and Column Decoder
.
Alternate Data Input
IH1min
IH1min
DDmax
DDmax
: This implies I/O current is not considered. The device is
: This implies I/O current is not considered. The device is
and at maximum CPU clock frequency with all outputs
and at maximum CPU clock frequency with all outputs
CPU
CPU
Clock
Latch
Input
CPU
Test Mode
is expressed in MHz). This dependency is
is expressed in MHz). This dependency is
Figure
is expressed in MHz). This dependency is
Output
Buffer
44.
P2.0
CC0IO
ST10F276E
DD
-