MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1162

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Global Utilities
19.3
The following subsections provide information about signals that serve as global utilities.
19.3.1
Table 19-1
19.3.2
Table 19-2
19-2
CKSTP_IN
ASLEEP
Signal
External Signal Description
Signal Name
CKSTP_OUT
summarizes the external signals used by the global utilities block.
describes the global utilities block signals in detail.
GPOUT[0:7]
Signals Overview
Detailed Signal Descriptions
CKSTP_IN
CLK_OUT
ASLEEP
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O
I
Asleep. See
device completes its power-on reset sequence and reaches its ready state.
Checkstop in
Meaning
Meaning
Timing Assertion—May occur at any time; may be asserted asynchronously to the input clocks.
Timing Assertion—May occur at any time; may be asserted asynchronously to the input clocks.
State
State
I/O
O
O
O
O
I
Asserted—Indicates that the device is either still in its power-on reset sequence or it has
Negated—The device is not in sleep mode. (It has either awakened from a power-down state,
Negation—Negates synchronously with SYSCLK when leaving power-on sequence;
Asserted—Indicates that the e500 core must enter a hard stop condition. All e500 clocks are
Negated—Indicates that normal operation should proceed.
Negation—Must remain asserted until the MPC8533E is reset with assertion of HRESET.
Section 19.5.1.5.3, “Sleep
Signals that the device has reached a sleep state.
Checkstop input
Checkstop output.
Clock out. Selected by CLKOCR values.
General-purpose output.
reached a sleep state after a power-down command is issued by software.
or has completed the POR sequence.)
otherwise negation is asynchronous.
turned off. CKSTP_OUT is asserted. The rest of MPC8533E device logic, including
memory controllers, internal memories and registers, and I/O interfaces, remains
functional.
Table 19-2. Detailed Signal Descriptions
Table 19-1. External Signal Summary
Description
Mode.” After negation of HRESET, ASLEEP is asserted until the
Description
Reference (Section/page)
Table 19-2 on page 19-2
Table 19-2 on page 19-2
19.5.1.5.3/19-28
19.4.1.23/19-23
19.4.1.9/19-12
Freescale Semiconductor