MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 422

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
10.3.2.5
The global timer destination register controls the destination processor for this timer’s interrupt, as shown
in
Table 10-19
10.3.2.6
The timer control register (TCR) shown in
count frequency and roll-over behavior.
There are two choices for the clock source for the timers: a selectable frequency ratio from the CCB clock,
or the RTC signal. The TCR also provides the ability to create timers larger than the default 31-bit global
timers. Timer cascade fields allow configuration of up to two 63-bit timers, one 95-bit timer or one 127-bit
timer.
With one exception mentioned below, the value reloaded into a timer is determined by its roll-over control
field TCR[ROVR]. Setting a timer’s roll-over field causes its current count register to roll over to all ones
when the count reaches zero. This is equivalent to reloading the count register with 0xFFFF_FFFF instead
of its base count value. Clearing a timer’s associated ROVR bit ensures the timer always reloads with its
base count value.
When timers are cascaded the last (most significant) counter in the cascade also affects their roll-over
behavior. Cascaded timers always reload their base count when the most significant counter has
decremented to zero, regardless of the settings in TCR[ROVR].
For example, timers 0, 1, and 2 can be cascaded to generate one interrupt every hour. As shown in
Table
clock, (TCR[CLKR] = 0 sets a clock ratio of 8), provides a basic input of 41.625 MHz to timer 0. Setting
timer 0 to count 41,625,000 (0x27B_25A8) timer clock cycles will generate one output per second. Setting
both timers 1 and 2 to 59, and cascading all three timers, generates one interrupt every hour from timer 2.
10-26
0–30
Bits Name
Offset 0x4_1130, 0x4_1170, 0x4_11B0, 0x4_11F0
Reset 0
31
Figure
W
R
10-20, given a CCB clock of 333 MHz, letting the timer clock frequency default to 1/8
P0
—
0
10-15.
0
Reserved
Processor 0. Indicates that processor 0 handles any interrupt. This bit is meaningful only in a multi-core device. In
a single-core device, internally serviced interrupts are always directed to processor 0. Permanently set and read
only.
1 Interrupt directed to processor 0.
describes the GTDRn fields.
0
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Global Timer Destination Registers (GTDR n )
Timer Control Register (TCR)
0
0
0
Figure 10-15. Global Timer Destination Registers (GTDR n )
0
0
0
Table 10-19. GTDR n Field Descriptions
0
0
0
Figure 10-17
0
0
0
—
0
Description
0
provides various configuration options such as
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
0
Access: Read only
0
th
0
the system
0
30 31
0
P0
1