MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 257

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.13.1.2
Freescale Semiconductor
Reset
49–62
32–33
34–35
36–37
38–39
SPR 309
Bits
Bits
48
63
W
R
IAC1US IAC1ER IAC2US IAC2ER IAC12M
32
Name
IAC1US Instruction address compare 1 user/supervisor mode
IAC1ER Instruction address compare 1 effective/real mode
IAC2US Instruction address compare 2 user/supervisor mode
IAC2ER Instruction address compare 2 effective/real mode
RET
Name
FT
—
33
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Debug Control Register 1 (DBCR1)
Return debug event enable
0 RET debug events cannot occur
1 RET debug events can occur
Note: An rfci does not cause an RET debug event if MSR[DE] = 0 at the time that rfci executes.
Reserved, should be cleared.
Freeze timers on debug event
0 Enable clocking of timers
1 Disable clocking of timers if any DBSR bit is set (except MRR)
34
00 IAC1 debug events can occur
01 Reserved
10 IAC1 debug events can occur only if MSR[PR] = 0
11 IAC1 debug events can occur only if MSR[PR] = 1
00 IAC1 debug events are based on effective addresses
01 Reserved on the e500
10 IAC1 debug events are based on effective addresses and can occur only if MSR[IS] = 0
11 IAC1 debug events are based on effective addresses and can occur only if MSR[IS] = 1
00 IAC2 debug events can occur
01 Reserved
10 IAC2 debug events can occur only if MSR[PR] = 0
11 IAC2 debug events can occur only if MSR[PR] = 1
00 IAC2 debug events are based on effective addresses
01 Reserved on the e500
10 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 0
11 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 1
35
36
Table 6-35. DBCR0 Field Descriptions (continued)
37
Figure 6-51. Debug Control Register 1 (DBCR1)
38
Table 6-36. DBCR1 Field Descriptions
39
40
41
42
All zeros
Description
Description
—
Access: Supervisor read/write
Core Register Summary
6-41
63