MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 488

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.1.4.1
Processing begins when a descriptor pointer is written to the fetch FIFO of one of the channels. Based on the
services requested by the descriptor header, the channel asks the controller to assign the necessary EUs to that
channel. If all appropriate EUs are already reserved by other channels, the channel stalls and waits to fetch
data until an appropriate EU is available. If multiple channels simultaneously request the same EU, the EU
is assigned on a weighted priority or round-robin basis.
Once the required EU has been reserved, the channel requests that the controller fetch and load the
appropriate data. The controller acts as a master on the system bus, reading and writing on byte boundaries.
The channel operates the EU, and makes further requests to the controller to write output data to system
memory. When the descriptor processing is complete, the channel asks the controller to release the EU for
use by other channels.
12.1.4.2
All execution units (EUs) are memory-mapped, and can be used entirely through register read/write
access. The SEC operates as a slave, and the host must write the information typically provided through
the descriptor into the appropriate registers and FIFOs of the SEC. This method is more CPU intensive,
and requires a great deal of familiarity with the SEC registers. It is recommended that host-controlled
access be used only for operations using a single EU, and for debug purposes.
For more information, refer to
12.2
Table 12-2
in the execution units. These address values are offsets from CCSRBAR.
Note that these tables show modulo-8 addresses; the three least-significant address bits that are used to
select bytes within 64-bit words are not shown.
12-10
0x3_0000–0x3_0FFF
0x3_1000–0x3_10FF
0x3_1100–0x3_11FF
0x3_1200–0x3_12FF
0x3_1300–0x3_13FF
0x3_1400–0x3_14FF
Address Offset
(AD 17–0)
Configuration of Internal Memory Space
shows the base address map, while
Channel-Controlled Access
Host-Controlled Access
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Channel_1 Channel 1
Channel_2 Channel 2
Channel_3 Channel 3
Channel_4 Channel 4
Controller
Module
—
Section 12.6, “Security Controller.”
Table 12-2. SEC Base Address Map
Reserved
Arbiter/controller control register space
Table 12-3
Description
provides the address map, including all registers
Resource control
Data control
Type
—
Freescale Semiconductor
12.6/12-104
Reference
12.5/12-91
—