MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 420

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1–31 COUNT Current count. Decremented while GTBCR n [CI] is zero. When the timer count reaches zero, an interrupt is
Programmable Interrupt Controller
Table 10-15
0–31 FREQ Timer frequency (in ticks/second (Hz)). Used to communicate the frequency of the global timers’ clock source,
10.3.2.2
The global timer current count registers (GTCCRs), shown in
each of the four PIC timers.
Table 10-16
10.3.2.3
The global timer base count registers (GTBCRs) contain the base counts for each of the four PIC timers as
shown in
reaches zero. Note that when zero is written to the base count field, (and GTCCRn[CI] = 0), the timer
generates an interrupt on every timer cycle.
10-24
Bits
Bits Name
0
Offset 0x4_1100, 0x4_1140, 0x4_1180, 0x4_11C0
Reset
Offset 0x4_1110, 0x4_1150, 0x4_1190, 0x4_11D0
Reset 1
W
R TOG
W
Name
R
TOG
CI
0
0
Figure
1
0
identically the core complex bus (CCB) clock, to user software. See
TFRR is set only by software for later use by other applications and its value in no way affects the operating
frequency of the global timers. The timers operate at a ratio of this clock frequency set by TCR[CLKR]. See
Section 10.3.2.6, “Timer Control Register (TCR).”
Toggle. Toggles when the current count decrements to zero. Cleared when GTBCR n [CI] goes from 1 to 0.
generated (provided it is not masked), the toggle bit is inverted, and the count is reloaded. For non-cascaded
timers, the reload value is the contents of the corresponding base count register. Cascaded timers are reloaded
with either all ones, or the contents of the base count register, depending on the value of TCR[ROVR]. See
Section 10.3.2.6, “Timer Control Register (TCR),”
describes the TFRR register.
describes the GTCCRn fields.
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Global Timer Current Count Registers (GTCCR n )
Global Timer Base Count Registers (GTBCR n )
10-13. This value is reloaded into the corresponding GTCCRn when the current count
0
0
Figure 10-12. Global Timer Current Count Registers (GTCCR n )
0
Figure 10-13. Global Timer Base Count Register (GTBCR n )
0
0
Table 10-16. GTCCR n Field Descriptions
0
Table 10-15. TFRR Field Descriptions
0
0
0
0
0
0
All zeros
BASE CNT
Description
for more details.
Description
0
COUNT
0
0
Figure
0
0
Section 4.4.4, “Clocking,”
10-12, contain the current count for
0
0
0
0
0
Freescale Semiconductor
0
0
Access: Read/Write
for more details.
Access: Read only
0
0
0
0
31
31
0