SC16C650BIB48 NXP Semiconductors, SC16C650BIB48 Datasheet - Page 21

• Manufacturer Part Number: SC16C650BIB48
• Description: UART, 32BYTE FIFO, 16C650, LQFP48
• Manufacturer: NXP Semiconductors

Specifications of SC16C650BIB48

• No. Of Channels: 1
• Data Rate: 3Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Automatic Software/Hardware Flow Control, Programmable Xon/Xoff Characters
• Rohs Compliant: Yes

NXP Semiconductors
SC16C650B_4
Product data sheet
7.4 Interrupt Status Register (ISR)
The SC16C650B provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is
cleared. However, it should be noted that only the current pending interrupt is cleared by
the read. A lower level interrupt may be seen after re-reading the interrupt status bits.
Table 13 “Interrupt source”
levels and the interrupt sources associated with each of these interrupt levels.
Table 13.
Table 14.
Priority
level
1
2
2
3
4
5
6
Bit
7:6
5:4
3:1
0
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
0
0
0
0
0
0
1
Interrupt source
Interrupt Status Register bits description
0
0
0
0
0
1
0
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not being
used. They are set to a logic 1 when the FIFOs are enabled.
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see
INT status.
Rev. 04 — 14 September 2009
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine.
logic 1 = no interrupt pending (normal default condition)
0
0
1
0
0
0
0
shows the data values (bits 0:5) for the six prioritized interrupt
UART with 32-byte FIFOs and IrDA encoder/decoder
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
Table
LSR (receiver Line Status
Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal) /
Special character
CTS, RTS change of state
13).
SC16C650B
© NXP B.V. 2009. All rights reserved.
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