M52S128168A-7.5TG ELITE SEMICONDUCTOR, M52S128168A-7.5TG Datasheet - Page 14

• Manufacturer Part Number: M52S128168A-7.5TG
• Description: IC, SDRAM, 128MBIT, 133MHZ, TSOP-54
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5TG

• Memory Type: DRAM - Sychronous
• Memory Configuration: 2M X 16
• Ic Interface Type: Parallel
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Frequency: 133MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Page Size: 128MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
DEVICE OPERATIONS (Continued)
AUTO PRECHARGE
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy t
and CAS latency. The auto precharge command is issued at
the same time as burst write by asserting high on A10/AP,
the bank is precharge command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
BOTH BANKS PRECHARGE
A11 banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS , and
(min)
end of t
state.
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on CS , RAS and CAS with high on CKE
and WE . The auto refresh command can only be asserted
with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by t
required can be calculated by driving t
time and them rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us.
Elite Semiconductor Memory Technology Inc.
WE with high on A10/AP after all banks have satisfied t
requirement, performs precharge on all banks. At the
RP
after performing precharge all, all banks are in idle
RAS (min)
RFC (min)
and “t
. The minimum number of clock cycles
RP
” for the programmed burst length
RFC
with clock cycle
RAS
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode
for data retention and low power operation of SDRAM.
In self refresh mode, the SDRAM disables the internal
clock and all the input buffers except CKE. The refresh
addressing and timing is internally generated to reduce
power consumption. The self refresh mode is entered
from all banks idle state by asserting low on CS ,
refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored
to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed
by NOP’s for a minimum time of t
reaches idle state to begin normal operation.
RAS , CAS and CKE with high on WE . Once the self
Publication Date: Oct. 2007
Revision: 1.1
M52S128168A
RFC
before the SDRAM
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