M52S128324A-7BG ELITE SEMICONDUCTOR, M52S128324A-7BG Datasheet
M52S128324A-7BG
Specifications of M52S128324A-7BG
Related parts for M52S128324A-7BG
M52S128324A-7BG Summary of contents
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... Revision 1.1(Jun. 20 2006) -Modify tRC and tRFC spec Revision 1.2(Mar. 02 2007) - Delete BGA ball name of packing dimensions Revision 1.3 (Mar. 07, 2008) - Modify DC spec. - Modify t and t timing SAC SHZ Elite Semiconductor Memory Technology Inc. M52S128324A Publication Date: Mar. 2008 Revision: 1.3 1/47 ...
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... Elite Semiconductor Memory Technology Inc. M52S128324A Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION MAX Product No. PACKAGE COMMENTS FREQ. M52S128324A-7TG 143MHz 86 TSOPII M52S128324A-7BG 143MHz 90 FBGA Publication Date: Mar. 2008 Revision: 1.3 Pb-free Pb-free 2/47 ...
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... CAS L VDDQ DQ8 VSS VDD M VSSQ DQ10 DQ9 DQ6 N VSSQ DQ12 DQ14 DQ1 P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD M52S128324A 8 9 DQ16 VSSQ A0 A1 BA1 A11 CS RAS DQM0 WE DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ DQ0 DQ2 Publication Date: Mar. 2008 Revision: 1 ...
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... Enables row access & precharge. Latches column address on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. M52S128324A DQM0~3 DQ Publication Date: Mar. 2008 Revision: 1.3 4/47 ...
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... ≤ 3ns acceptable. ≤ 3ns acceptable 0.3V, all other pins are not under test = 0V. DD ≤ OUT DD M52S128324A INPUT FUNCTION after the clock and masks the output. SHZ Value Unit -1.0 ~ 3.6 V -1.0 ~ 3.6 V ° -55 ~ +150 ° ) Max Unit Note 2.7 ...
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... CKE V (min), CLK V (max), tcc = IH IL input signals are stable IOL = 0 mA Page Burst 2 Banks activated CK(min) ≥ RC(min) ≤ CKE 0.2V ≤ CKE 0.2V M52S128324A Min Max CAS Version Latency -7 90 0.8 0.6 = 10ns cc 25 ∞ ∞ 10 120 ...
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... Output ( Version Symbol - RRD(min RCD(min RP(min RAS(min) t (max) 100 RAS t 70 RC(min RFC(min CDL(min RDL(min BDL(min) M52S128324A = ° Unit Vtt = 0.5xV Ω Ω (Fig Output Load Circuit Unit Note CLK 2 CLK 2 CLK 2 Publication Date: Mar. 2008 Revision: 1.3 DDQ 7/47 ...
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... If tr & longer than 1ns. transient time compensation should be considered. i.e., [(tr + tf)/2 – should be added to the parameter. Elite Semiconductor Memory Technology Inc. Version Symbol - CCD(min Symbol Min 7 t 8.6 1000 SAC - 2 2 SLZ - t - SHZ - M52S128324A Unit Note CLK Unit Note Max 1 Publication Date: Mar. 2008 Revision: 1.3 8/47 ...
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... BA1 BA0 A10 Elite Semiconductor Memory Technology Inc Address bus TCSR PASR Extended Mode Register Set PASR TCSR DS M52S128324A x =Don’t care A2-A0 WT=0 000 Full Array 001 1/2 of Full Array 010 1/4 of Full Array 011 R 100 R 101 R 110 R 111 R A4-A3 Max ...
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... If both BA1 is “Low” and BA0 is “High” at read ,write , row active and precharge ,bank B is selected. Elite Semiconductor Memory Technology Inc. CKEn-1 CKEn CS RAS CAS Entry Exit Entry Exit Valid , X = Don’t Care Logic High , L = Logic Low ) M52S128324A SIMPLIFIED TABLE DQM BA0,1 A10/ CODE Row Address ...
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... RP A10/ RFU W.B.L TM CAS Latency Burst Type Latency Reserved Reserved Reserved Reserved Reserved M52S128324A CAS Latency BT Burst Length Type Sequential Interleave Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Full Page Length : 256 Publication Date: Mar. 2008 Revision: 1 ...
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... ESMT BURST SEQUENCE (BURST LENGTH = 4) Initial Address BURST SEQUENCE (BURST LENGTH = 8) Initial Elite Semiconductor Memory Technology Inc. Sequential Sequential M52S128324A Interleave Interleave Publication Date: Mar. 2008 Revision: 1 12/47 ...
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... The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t clock and then rounding of the result to the next higher integer. M52S128324A RAS and from the time of bank activation. with cycle time of the RCD (min) Publication Date: Mar. 2008 Revision: 1 ...
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... Four banks can be precharged at the same time by using Precharge all command. Asserting low RAS , and WE with high on A10/AP after all banks have satisfied t banks. At the end of t banks are in idle state. M52S128324A is satisfy from the RAS (min) RP (max). Therefore, RAS and “t ” ...
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... NOP’s for a minimum time of t reaches idle state to begin normal operation recommended to use burst 40% auto refresh cycles immediately recommended to use burst 4096 auto refresh cycles immediately before and after exiting self refresh. M52S128324A before the SDRAM RC before and after self refresh, Publication Date: Mar ...
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... Mode register set command ( CS , RAS , CAS , WE = Low) The M52S128324A has a mode register that defines how the device operates. In this command, A0 through A10 and BA0~BA1 are the data input pins. After power on, the mode register set command must be executed to initialize the device. ...
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... Before executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During t period (from refresh command to refresh or activate command), the RC M52S128324A cannot accept any other command. Elite Semiconductor Memory Technology Inc. M52S128324A CLK H CKE ...
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... CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M52S128324A exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. ...
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... CLOCK Suspend DQM Operation *Note : 1. CKE to CLK disable/enable = 1CLK. 2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”. 3. DQM masks both data-in and data-out. Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1.3 19/47 ...
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... By “interrupt” is meant to stop burst read/write by external before the end of burst. By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write CAS to CAS delay. (=1CLK) CCD Last data in to new column address delay. (=1CLK) CDL Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1.3 20/47 ...
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... ESMT 4. CAS Interrupt (II) : Read Interrupted by Write & DQM ( Elite Semiconductor Memory Technology Inc M52S128324A D 3 Publication Date: Mar. 2008 Revision: 1.3 21/47 ...
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... To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1.3 22/47 ...
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... The row active command of the precharge bank can be issued after t The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc M52S128324A from this point. ...
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... CLK ; Last data in to burst stop delay. BDL 3. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely. 4. PRE : All banks precharge, if necessary. MRS can be issued only at all banks precharge state. Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1.3 24/47 ...
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... Before/After self refresh mode, burst auto refresh (40% cycles) is recommended. Before/After self refresh mode, burst auto refresh (4096 cycles) is recommended. Elite Semiconductor Memory Technology Inc from self refresh exit command, any other command can not be accepted. M52S128324A Publication Date: Mar. 2008 Revision: 1.3 25/47 ...
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... During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. M52S128324A Publication Date: Mar. 2008 Revision: 1.3 26/47 ...
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... NOP (Continue Burst to End NOP (Continue Burst to End ILLEGAL X BA CA, A10/AP ILLEGAL X BA RA, RA10 ILLEGAL ILLEGAL M52S128324A ACTION Row Active) Row Active) Row active Row Active) Row Active) Row active Precharge) Precharge) Precharge) Precharge) Publication Date: Mar. 2008 Revision: 1.3 27/47 Note ...
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... NOP ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address M52S128324A ACTION Idle after t RP Idle after t RP Idle after t RDL Row Active after t RCD Row Active after t RCD Idle after t RC Idle after t RC Idle after 2clocks Idle after 2clocks AP = Auto Precharge Publication Date: Mar ...
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... Refer to Operations in Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend must be satisfy before any command other than exit. SS M52S128324A ACTION Note Idle after t (ABI Idle after t (ABI ABI 7 ABI Publication Date: Mar. 2008 Revision: 1.3 ...
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... ESMT Single Bit Read-Write-Read Cycle(Same Page) @ CAS Latency = 3,Burst Length = Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1 30/47 ...
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... Enable auto precharge , precharge bank B at end of burst. 0 Enable auto precharge , precharge bank C at end of burst. 1 Enable auto precharge , precharge bank D at end of burst. Precharge 0 Bank A 1 Bank B 0 Bank C 1 Bank D X All Banks M52S128324A Publication Date: Mar. 2008 Revision: 1.3 31/47 ...
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... ESMT Power Up Sequence Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1.3 19 32/47 ...
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... Qa0 Qa1 Qa2 Qa3 *Note3 Qa1 Qa0 Qa2 Qa3 Precharge Row Active (A-Ban k) (A- Bank) ) after the clock. SHZ M52S128324A Db2 Db1 Db3 Db0 Db1 Db0 Db2 Db3 *Note3 W rite (A- Bank) Publication Date: Mar. 2008 Revision: 1 RDL t RDL Precharge (A-Bank) ...
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... Row precharge will interrupt writing. Last data input , t 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc Read ( A - Bank ) before row precharge , will be written. RDL M52S128324A Write Write ...
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... Note can be don’t cared when RAS , CAS and WE are high at the clock high going edge interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1 35/47 ...
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... To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data interrupt burst write by Row precharge , both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1 36/47 ...
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... Read & Write Cycle at Different Bank @ Burst Length = Row Active Read (A-Bank) (A-Bank) *Note : 1. t should be met to complete write. CDL 2. t should be met. RCD Elite Semiconductor Memory Technology Inc Precharge (A-Bank) Row Active (D-Bank) M52S128324A Row Active (B-Bank) Publication Date: Mar. 2008 Revision: 1 37/47 ...
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... Read & Write cycle with Auto Precharge @ Burst Length = Row Active ( A - Bank ) Row Active ( D - Bank ) *Note : 1. t should be controlled to meet minimum t CDL (In the case of Burst Length = 1 & 2) Elite Semiconductor Memory Technology Inc Read with Auto Precharge Bank ) before internal precharge start. RAS M52S128324A Publication Date: Mar. 2008 Revision: 1 38/47 ...
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... ESMT Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = *Note : 1. DQM is needed to prevent bus contention should be met. RCD Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1 39/47 ...
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... Both cases are illustrated above timing diagram. See the lable 1,2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycles”. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1 ...
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... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc M52S128324A Publication Date: Mar. 2008 Revision: 1 ...
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... Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = *Note: 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + t Elite Semiconductor Memory Technology Inc prior to Row active command. SS M52S128324A Publication Date: Mar. 2008 Revision: 1 42/47 ...
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... CKE going high to complete self refresh exit cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Elite Semiconductor Memory Technology Inc required before exit from self refresh. RAS M52S128324A Publication Date: Mar. 2008 Revision: 1 ...
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... CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M52S128324A Publication Date: Mar ...
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... BSC 0.61 REF 11.76 BSC 10.16 BSC 0.50 0.60 0.80 REF 0.50 BSC 0.25 ° 8 ° ° ° ° M52S128324A Dimension in inch Min Norm Max 0.047 0.002 0.004 0.006 0.037 0.039 0.011 0.007 0.018 0.007 0.008 0.009 0.005 0.008 ...
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... M52S128324A Norm Max 0.055 0.016 0.035 0.037 0.020 0.315 0.319 0.512 0.516 0.252 0.441 0.031 Publication Date: Mar. 2008 Revision: 1.3 46/47 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52S128324A Publication Date: Mar. 2008 Revision: 1.3 47/47 ...