M52S128324A-7BG ELITE SEMICONDUCTOR, M52S128324A-7BG Datasheet - Page 26

• Manufacturer Part Number: M52S128324A-7BG
• Description: IC, SDRAM, 128MBIT, 143MHZ, FBGA-90
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128324A-7BG

• Memory Type: DRAM - Sychronous
• Memory Configuration: 2M X 16
• Ic Interface Type: Parallel
• Memory Case Style: FBGA
• No. Of Pins: 90
• Operating Temperature Range: 0°C To +70°C
• Frequency: 133MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Page Size: 128MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
12. About Burst Type Control
13. About Burst Length Control
Elite Semiconductor Memory Technology Inc.
Random
Random
Interrupt
MODE
MODE
MODE
MODE
MODE
Basic
Basic
Random Column Access
Sequential Counting
(Interrupted by
RAS Interrupt
CAS Interrupt
Interleave Counting
Precharge)
Burst Stop
Full Page
t
CCD
1
2
4
8
= 1 CLK
At MRS A210 = “000”
At auto precharge . tRAS should not be violated.
At MRS A210 = “001”
At auto precharge . tRAS should not be violated.
At MRS A210 = “010”
At MRS A210 = “011”
At MRS A210 = “111”
At the end of the burst length , burst is warp-around.
t
Using burst stop command, any burst length control is possible.
Before the end of burst. Row precharge command of the same bank stops read /write burst
t
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
with auto precharge.
BDL
RDL
= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
= 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Publication Date: Mar. 2008
Revision: 1.3
M52S128324A
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