M52S128324A-7BG ELITE SEMICONDUCTOR, M52S128324A-7BG Datasheet - Page 41

IC, SDRAM, 128MBIT, 143MHZ, FBGA-90

M52S128324A-7BG

Manufacturer Part Number
M52S128324A-7BG
Description
IC, SDRAM, 128MBIT, 143MHZ, FBGA-90
Manufacturer
ELITE SEMICONDUCTOR
Datasheet

Specifications of M52S128324A-7BG

Memory Type
DRAM - Sychronous
Memory Configuration
2M X 16
Ic Interface Type
Parallel
Memory Case Style
FBGA
No. Of Pins
90
Operating Temperature Range
0°C To +70°C
Frequency
133MHz
Filter Terminals
SMD
Rohs Compliant
Yes
Page Size
128MB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
C L O C K
A 1 0 / A P
A D D R
ESMT
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
Elite Semiconductor Memory Technology Inc.
C K E
D Q M
C A S
R A S
B A 1
B A 0
W E
D Q
C S
2. Burst stop is valid at every burst length.
R o w A c t i v e
0
( A - B a n k )
AC parameter of t
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
R A a
R A a
1
2
3
( A - B a n k )
RDL
W r i t e
D A a 0 D A a 1
C A a
.
4
5
D A a 2 D A a 3 D A a 4
6
7
B u r s t S t o p
8
9
t
B D L
H I G H
1 0
( A - B a n k )
W r i t e
D A b 0
C A b
1 1
D A b 1
1 2
D A b 2
1 3
D A b 3 D A b 4 D A b 5
1 4
Publication Date: Mar. 2008
Revision: 1.3
M52S128324A
1 5
1 6
* N o t e 1
t
R D L
1 7
P r e c h a r g e
( A - B a n k )
1 8
: D o n ' t C a r e
41/47
1 9

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